## Using Viewlogic MOTIVE & MOTIVE for Powerview Software with MAX+PLUS II Software

The following topics describe how to use the Viewlogic MOTIVE and MOTIVE for Powerview software with MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment

- Software Requirements
- MAX+PLUS II/Viewlogic Powerview Interface File Organization
- MAX+PLUS II/Viewlogic Powerview Project File Structure

### Timing Verification

- Timing Verification Flow
- Performing Timing Verification of EDIF Output Files (.edo) with MOTIVE & MOTIVE for Powerview Software
- Performing Timing Verification of Verilog Output Files (.vo) with MOTIVE Software

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Viewlogic Powerview Graphical User Interface & the Altera Toolbox
- Powerview Command-Line Syntax
- Compiling Projects with MAX+PLUS II Software
- Programming Altera® Devices

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Viewlogic web site (http://www.Viewlogic.com)

## Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment

To use the MAX+PLUS® II software with Viewlogic's Powerview software, you must install the MAX+PLUS II software, familiarize yourself with the Altera® Toolbox in the Powerview Cockpit, and then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Viewlogic Powerview interface is installed automatically when you install the MAX+PLUS II software on your workstation.

To set up your working environment for the MAX+PLUS II/Viewlogic Powerview interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Viewlogic software versions described in MAX+PLUS II/Viewlogic Powerview Software Requirements.

2. Add the following environment variable to your .cshrc file to specify /usr/maxplus2 as the MAX+PLUS II system directory:

   `setenv ALT_HOME /usr/maxplus2`

3. Add the $ALT_HOME/Viewlogic/standard, $ALT_HOME/bin, and $ALT_HOME/Viewlogic/bin directories to the `PATH` environment variable in your .cshrc file.

4. Add the $ALT_HOME/Viewlogic/standard directory to the `WDIR` environment variable in your .cshrc file using the following syntax:

   `setenv WDIR $ALT_HOME/Viewlogic/standard:/<`Powerview system directory>`/standard`

   | Make sure the $ALT_HOME/Viewlogic/standard directory is the first directory in your `WDIR` path.

5. Source your .cshrc file by typing `source .cshrc` at the UNIX prompt.

6. Create the Viewlogic Powerview viewdraw.ini configuration file.

7. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:

   `cp /usr/maxplus2/maxplus2.ini $HOME`

   `chmod u+w $HOME/maxplus2.ini`

   | The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as MAX+PLUS II symbol and logic function library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.

   Normally, you do not have to edit your local copy of maxplus2.ini, because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

8. If you plan to instantiate Library of Parameterized Modules (LPM) functions in ViewDraw schematics, you must create a new file with the name vdraw.vs. The vdraw.vs file must include the following line:

   `load ("vdpath")`

   You must also make sure that you specify the vdraw.vs file in your `WDIR` path.

9. Set up a directory structure that facilitates working with the MAX+PLUS II/Viewlogic Powerview interface. Refer to MAX+PLUS II/Viewlogic Powerview Project File Structure.

| Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Viewlogic Powerview Interface File Organization for information about the MAX+PLUS II/Viewlogic Powerview directories that are created during MAX+PLUS II installation.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Viewlogic Software Requirements

The following applications and utilities are used to generate, process, synthesize, and verify a project with MAX+PLUS® II and Viewlogic software.

Viewlogic | Altera
--- | ---
VHDL Analyzer | ViewTrace | MAX+PLUS II version 10.0
Vantage VHDL Analyzer | ViewData Path |
VHDL -> sym | MOTIVE version 5.1.6 |
edifneto | SDF2MTV (optional) |
edifneti | Fusion/VCS |
EEDIF (optional) | vsm |
MMP (optional) | ViewPath (optional) |

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Viewlogic applications the current version of the MAX+PLUS II software supports. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

## MAX+PLUS II/Viewlogic Powerview Interface File Organization

Table 1 shows the MAX+PLUS® II/Viewlogic Powerview interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation.

| For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

#### Table 1. MAX+PLUS II Directory Organization

Directory | Description
--- | ---
./lmf | Contains the Altera-provided Library Mapping File, vwlogic.lmf, that maps Viewlogic logic functions to equivalent MAX+PLUS II logic functions.
./Viewlogic | Contains the alt_edif.cfg EDIF configuration file that is used with the edifneti utility. Also contains the library and sample subdirectories.
./Viewlogic/examples | Contains the sample Viewlogic designs.
./Viewlogic/library/max2sim | Contains the MAX+PLUS II simulation model library (max2_sim) for use in ViewSim software.
./Viewlogic/library/alt_max2 | Contains MAX+PLUS II primitives (`EXP`, `GLOBAL`, `LCELL`, `SOFT`, `CARRY`, `CASCADE`, `DFFE`, `DFFE6K`, and `OPNDRN`), macrofunctions (`a_8fadd`, `a_8mcomp`, `a_8count`, `a_81mux`), and megafunctions (`clklock`) for use in ViewDraw schematics. These logic functions support specific architectural features of Altera® devices. The alt_max2 library also contains modified versions of the ViewDraw primitives that use tri-state buffers, because these primitives require special handling in the MAX+PLUS II/Viewlogic Powerview interface.
./Viewlogic/library/synlib | Contains the Altera-provided synthesis library altera, which includes MAX+PLUS II primitives, the altera.sml file, a sym directory, and a wir directory for use with ViewSynthesis software.
./Viewlogic/library/alt_mf | Contains the VHDL models for the MAX+PLUS II primitives (`EXP`, `GLOBAL`, `LCELL`, `SOFT`, `CARRY`, `CASCADE`, `DFFE`, and `OPNDRN`), macrofunctions (`clklock`) for use with ViewSynthesis software, the Vantage VHDL Analyzer software, and the VHDL source files. These logic functions are used to maintain portability to other architectures.
./Viewlogic/library/alt_time | Contains MOTIVE timing models for MAX+PLUS II logic functions (motive.lib), including the `clklock` megafunction, and MAX+PLUS II driver models (motive.drv).
./Viewlogic/library/alt_vtl | Contains the VHDL source files for the VITAL 3.0-compliant library. This library is available for ViewSim software.
./Viewlogic/bin | Contains all MAX+PLUS II, Viewlogic, and interface-related scripts.
./Viewlogic/standard | Contains all standard .ini files and standard tools.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Viewlogic Powerview Project File Structure

In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an Altera® Hardware Description Language (AHDL) TDF; or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by Powerview and imported into the MAX+PLUS II software as an EDIF Input File (.edf). Figure 1 shows an example of MAX+PLUS II project directory structure that includes Powerview-generated files.

#### Figure 1. Sample MAX+PLUS II Project Organization

The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

Unlike Powerview, the MAX+PLUS II software does not automatically create a project directory when you create a project. A single directory can contain several MAX+PLUS II design files, and you can specify any one of the designs in the directory as a project in the MAX+PLUS II software.

### Viewlogic Powerview Local Work Area Structure

When you create a project with the Powerview Cockpit's Create command (Project menu), the project directory is created. You should generate design files and functional simulation files under this directory. A max2 subdirectory is automatically created under your current project directory when you generate an EDIF file from your schematic or VHDL file. The <project name>.edf file is stored in the max2 subdirectory. All MAX+PLUS® II Compiler output files are created in the /<project name>/max2 subdirectory.

| ViewDraw files are identified by their directories and not by their extensions, so it is easy to overwrite files unintentionally. To avoid overwriting files, Altera recommends that you create a new project directory, <project name>/max2/sim, where you can generate all the files needed for simulation.

### ViewDraw Project File Structure

Each ViewDraw project directory contains three subdirectories: wir, sch, and sym. See Table 1.

#### Table 1. ViewDraw Subdirectories

Directory | Topics
--- | ---
./wir | Wirelist files that contain connectivity information for a particular logic block
./sch | Schematics that contain logic
./sym | Symbol files that are the ViewDraw graphical representation of the logic blocks

Each file type uses the filename extension .1. Different file types are distinguished only by their directory: /lib/wir/<project name>.1 is a wirelist file; /lib/sch/<project name>.1 is the corresponding schematic file; and /lib/sym/<project name>.1 is the corresponding symbol.

### VHDL Project File Structure

Each VHDL project directory contains three subdirectories. See Table 2.

#### Table 2. VHDL Subdirectories

Directory | Topics
./synth | All synthesis-related files and directories
./synth/<entity> | Four types of files: <entity>.pdf, <entity>.opt, <entity>.sta, and <entity>.gnl
./wir | Wirelist for synthesized VHDL modules

| For each VHDL entity in the design, there is a corresponding ./synth/<entity> directory.

## MAX+PLUS II/Viewlogic Powerview Timing Verification Flow

Figure 1 shows the timing verification flow for the MAX+PLUS® II/Viewlogic Powerview interface.

#### Figure 1. MAX+PLUS II/Viewlogic Powerview Project Timing Verification Flow

## Performing Timing Verification of EDIF Output Files (.edo) with MOTIVE & MOTIVE for Powerview Software

After you have compiled a project and generated an EDIF Output File (.edo) with the MAX+PLUS® II software, you can use Viewlogic MOTIVE or MOTIVE for Powerview software to perform timing verification. The max2_MOTIVE tool is located in both the Altera® Toolbox Design Tools Drawer and the Altera Toolbox Max2 Express Drawer. The MOTIVE timing model library, motive.lib, provides models of basic primitives and the `clklock` megafunction for timing verification.

To perform timing verification for EDIF Output Files with MOTIVE or MOTIVE for Powerview software, follow these steps:

1. Set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Generate an EDIF Output File (.edo) by compiling your design with the MAX+PLUS II software, as described in Compiling Projects with MAX+PLUS II Software.

3. Start the MOTIVE for Powerview software by double-clicking Button 1 on the max2_MOTIVE icon in the Altera Toolbox Design Tools Drawer. The MOTIVE for Powerview Control Panel opens.

4. Choose Setup Environment (File menu) to open the Environment Parameters dialog box, and specify the following options:

   1. Specify the directory for the Project Directory option.

   2. Specify /usr/maxplus2/vwlogic/library/alt_time/motive.lib for the Model Library Search Path option.

   3. Select EDIF for the Netlist Input Format option.

   4. Choose Accept. The MOTIVE for Powerview software automatically creates a tim subdirectory, which contains MOTIVE design cases and related files, in the current working directory.

5. Choose Save Parameters (File menu) to save your customized project setup.

6. To specify the project name, choose the New Design button to open the Adding a New Design dialog box. Type the design name in the New Design box. Choose Accept, then Dismiss.

7. To specify the case name, choose the New Case button to open the Adding a New Case dialog box. Type the case name in the New Case box. Select Default as the New Case Type. Choose Accept, then Dismiss.

8. Choose Browse Cases (File menu) to open the Case Display dialog box. In the Case Display dialog box, double-click Button 1 on the field that contains the case for the project. Double-clicking on the field opens a file manager listing all the project files located under that case. Choose Dismiss in the Case Display dialog box.

   1. Choose the Get File button from the file manager to display the Get File box at the bottom of the window. This box allows you to specify which file(s) you would like to add to the list of files for the current case.

   2. Type /<working directory>/<project name>`.edo` in the Get File box and choose Copy. The new file appears in the list of design files.

   3. Type /<working directory>/<project name>`.sdo` in the Get File box and choose Copy.

   4. Type /<working directory>/<project name>`.ref` in the Get File box and choose Copy.

   5. If your project contains memory functions, such as `ram`, `rom`, `dpram`, `scfifo`, `dcfifo`, `altdpram`, or `clklock`, type <project name>.vmo in the Get File box and choose Copy to add the MAX+PLUS II-generated VHDL Memory Model Output File (.vmo) to the list of files for the case. The MAX+PLUS II Compiler automatically generates this file for a project that contains memory functions.

      | Every MOTIVE analysis requires a MOTIVE Clock Reference File (.ref). If the project is simple, you can create the file in the Setup Advisor. Otherwise, you must create the file in a text editor using MOTIVE syntax. For more information on the purpose, function, and syntax of MOTIVE Clock Reference Files, see the MOTIVE System Reference.

   6. Choose Dismiss.

9. Choose the Netlister button in the MOTIVE for Powerview Control Panel to open the EDIF Netlist Parameters dialog box. To create a FutureNet Format Netlist File (.pin) with the EEDIF Netlister for your design, follow these steps:

   1. Choose the Select Design button to open the Select Design dialog box.

   2. Double-click Button 1 on the project name to open the Select Case dialog box.

   3. Double-click Button 1 on the case name in the Select Case dialog box to open the Select File dialog box.

   4. Double-click Button 1 on the EDIF Output File, <project name>.edo, in the Select File dialog box.

   5. Select Keep for all Case Sensitivity options in the EDIF Netlist Parameters dialog box.

   6. Choose Accept, then Dismiss to close the EDIF Netlist Parameters dialog box.

10. Choose the SDF2MTV button in the Control Panel to open the SDF2MTV (MOTIVE SDF Reader) Parameters dialog box and specify the following options:

    1. Choose the Select button next to the SDF Filename box to open the Select File dialog box.

    2. Double-click Button 1 on the project's Standard Delay Format (SDF) Output File, <project name>.sdo, in the Select File dialog box. The SDF2MTV utility creates a MOTIVE Model Pre-Processor (MMP) Control File (.ctl) that allows you to annotate the parameterized library, and an Interconnect Delay Data File (.idd).

    3. Choose Accept, then Dismiss to close the Select File dialog box.

11. If your project contains `ram`, `rom`, `dpram`, `scfifo`, `dcfifo`, `altdpram`, or `clklock` megafunctions, use the genmtv utility to back-annotate the MMP Control File and to allow the MMP Control File to recognize the function. The input to the genmtv utility is the VHDL Memory Model Output File (.vmo) described above. From the /<working directory>/<project name>/<case name> directory, type the following command at the UNIX prompt:

    `genmtv` <project name>

12. If your project contains RAM or ROM functions and you turned on the Flatten Bus option in the MAX+PLUS II Compiler's EDIF Netlist Writer Settings dialog box when you compiled your project, you must edit the mem.lib file, i.e., the MOTIVE Model Pre-Processor timing library file created with the genmtv utility. You must remove bracket `[` `]` characters from all occurrences of the address bus, e.g., change `A[0]` to `A0`, in both the `INPUTS` and `MIXED` sections of every RAM and ROM cell definition in mem.lib.

13. Choose the MMP button from the Control Panel to open the MOTIVE Model Pre-processor (MMP) Parameters dialog box and specify the following options:

    1. Choose the Select button next to the MMP Ctl File box to open the Select File dialog box.

    2. Double-click Button 1 on the project's MMP Control File, <project name>.ctl, in the Select File dialog box.

    3. In the MOTIVE Model Pre-processor (MMP) Parameters dialog box, choose the Setup Model Libraries button to display boxes on the right side of the dialog box that allow you to list additional source model libraries. In one of these boxes, type the following path and filename:

       `/usr/maxplus2/vwlogic/library/alt_time/motive.drv`

    4. If your project contains RAM or ROM functions, repeat step 13c but specify the pathname of the mem.lib file created in step 12. For example:

       `/usr/maxplus2/`<working directory>`/..../`<case name>`/mem.lib`

    5. In the MOTIVE Model Pre-processor (MMP) Parameters dialog box, choose Accept, then Dismiss. The MMP utility creates a design-specific Timing Model Library File (.mod).

14. Choose the Analyze button from the Control Panel to expand the Control Panel.

15. Double-click Button 1 on the project name in the Select Design box in the Control Panel to open the Select Case box.

16. Select the specific case of the project in the Select Case box and double-click Button 1 on the case name to open MOTIVE software and its Setup Advisor. The Setup Advisor helps guide you through the following steps to set up and configure a case analysis:

    1. In the Setup Advisor window, choose the Continue button to open the Project Name Selection dialog box, which displays the project name.

    2. Choose the Begin analysis button to open the Checking for existing project dialog box.

    3. Choose Continue to open the Design Specific Flow(s) dialog box and set up the project through the Setup Advisor. The Design Name option lists the project filename.

    4. Choose Continue to open the Flow and Translation Selection dialog box.

    5. Select the Manual Translation Flow option to specify input files and the steps to perform in the timing verification flow for MOTIVE software. Choose Continue to open the Manual Flow Selection dialog box and specify the following options:

       Option: | Setting:
       Netlist/Pinlist | FutureNet (.pin)
       Parametric | OVI Verilog (.sdf)

       In the Other box, select Use available MOTIVE files to use the input files you created in previous steps. Choose Continue to open the FutureNet Pinlist Preparation dialog box.

    6. Type the project name in the Root Block box. Choose Continue to open the OVI Standard Parametric Back-annotation dialog box.

    7. Type <project name>.sdo in the OVI (SDF) back-annotation file box. Choose Continue to open the MOTIVE Model Compilation dialog box.

    8. Replace the entry in the Control file(s) box with <project name>`.ctl`. Type the following two filenames, which must be separated by a space, in the Libraries(s) box:

       `/usr/maxplus2/vwlogic/library/alt_time/motive.lib /usr/maxplus2/vwlogic/library/alt_time/motive.drv`

    9. If your project contains RAM or ROM functions, add the mem.lib file to the directories specified in step 16h.

    10. Choose Continue to open the Quick Definition of Existing MOTIVE Files dialog box. The <project name>.ref filename appears in the Clock Reference File (.ref) box.

    11. Replace the entry in the Design's (pre-compiled) Model File (.mod) box with <project name>.mod. Choose Continue to open the Congratulations dialog box.

    12. Choose Continue to open the Cleaning up dialog box after completing the Setup Advisor interview. Select Save under Project name to save your setup, and choose Continue to close the Setup Advisor window.

17. In the MOTIVE window, choose Verify (Analyze menu) and then choose Execute to start verification. To view the output files, choose Output Files (View menu).

## Performing Timing Verification of Verilog Output Files (.vo) with MOTIVE Software

After you have compiled a project and generated a Verilog Output File (.vo) with the MAX+PLUS II Software, you can use Viewlogic MOTIVE to perform timing verification. The MOTIVE timing model library, motive.lib, provides basic primitives and the `clklock` megafunction for timing verification.

To perform timing verification for Verilog Output Files with MOTIVE software, follow these steps:

1. Set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Generate a Verilog Output File by compiling your design with the MAX+PLUS II software, as described in Compiling Projects with MAX+PLUS II Software.

3. Start the MOTIVE software by typing `motive` at the UNIX prompt. The MOTIVE Session Log and Setup Advisor windows are displayed. Choose OK.

4. Choose Project on the vertical menubar in the Setup Advisor, then choose the Name (Select project name) tab and specify the name of the project for Project name. The directory in which you started MOTIVE will be selected automatically for Current directory. Choose Accept. MOTIVE then searches for the <project name>.stm file. If this is a new file, a message will appear in the Session Log window that mentions that MOTIVE found a license and the message `could not open the <project name>.stm file -- assuming a new design.`

5. Choose Flow from the vertical menubar, then choose the Type (Select flow type) tab. Select the Using Verilog and SDF option and choose Accept.

6. Choose Options from the vertical menubar, then choose the Options (Miscellaneous usage options) tab. If desired, specify a different value for the MOTIVE analysis cycle time option. Choose Accept.

7. Choose Verilog on the vertical menubar and specify the following Verilog HDL input options:

   1. Choose the Translate (Translate Verilog netlist file) tab. Specify the name of the MAX+PLUS II-generated Verilog Output File (.vo) for the Verilog netlist option. Choose the Common Options button to display the Common Options dialog box. Select the Special Options option and turn on the Skip Behavioral Constructs option. Type either `pinlist` or a period (`.`) for the Generated pin files option. Choose OK to close the Common Options dialog box and return to the Translate tab.

   2. Specify the location of the MAX+PLUS II-generated alt_max2.vo file for the Vendor module definition option. Choose the Translate button. The Process Execution Log & Tips dialog box displays the current status of the translation to .pin files. Choose OK after successful translation.

   3. Choose the Import (Confirm Adding hierarchical blocks) tab. Choose the Import Blocks button. The MOTIVE Interaction Log & Tips dialog displays the current import status. Choose OK after a successful completion.

   4. Select the Hierarchy (Configure hierarchy options) tab. Type the name of the rootblock for the Rootblock of design option, or choose the Find Rootblock button to display the rootblock name. Choose Accept.

8. Choose the Check (Review and/or build the netlist database) tab. Choose the Incremental Build button. The MOTIVE Interaction Log & Tips dialog displays the current build status. Choose OK after a successful completion.

9. Select SDF on the vertical menubar, then select the Translate (SDF model preparation) tab. Type <project name>`.sdo` for the SDF file option, making sure that you specify the .sdo extension. Type <project name>`.ctl` for the MPP control file name, and <project name>`.idd` for the IDD file name.

10. Choose the Process SDF File button.

11. If your project contains the `clklock` megafunction, use the genmtv utility to back-annotate the MPP Control File and to allow the MPP Control File to recognize the `clklock` function. The input to the genmtv utility is the Verilog netlist file (.vo). From the /<working directory>/<project name>/<case name> directory, type the following command at the UNIX prompt:

    `genmtv -v` <project name>

12. If your project contains RAM or ROM functions and you turned on the Flatten Bus option the MAX+PLUS II Compiler's Verilog Netlist Writer Settings dialog box when you compiled your project, you must edit the mem.lib file, i.e., the MOTIVE Model Pre-Processor timing library file generated with the genmtv utility. You must remove the bracket `[ ]` characters from all occurrences of the address bus, e.g., change `A[0]` to `A0`, in both the `INPUTS` and `MIXED` sections of every RAM and ROM cell definition in mem.lib.

13. Select the MPP (MOTIVE model compilation) tab. Type <project name>`.ctl` for the Control file option. Type `/usr/maxplus2/Viewlogic/library/alt_time/motive.lib /usr/maxplus2/Viewlogic/library/alt_time/motive.drv` for the Libraries option. If the project contains memory functions, you should also specify the location of the mem.lib file for the Libraries option. Type <project name>`.mod` for the Generated model file option and <project name>`.rcf` for the Revised control file option. Choose the RUN MMP button. The MOTIVE Execution Log & Tips dialog displays and shows the current status. Choose OK after a successful completion.

14. Select Save from the File menu in the Setup Advisor to write all the selections made so far to the <project name>.stm file.

15. Select Clock on the vertical menubar, then choose the File (Check reference file and timebase options) tab. The correct name of the Clock Reference File (.ref) should be displayed for the Clock reference file option. Choose Accept.

    | Every MOTIVE analysis requires a MOTIVE Clock Reference File. If the project is simple, you can create the file in the Setup Advisor. Otherwise, you must create the file with a text editor using MOTIVE syntax. For more information on the purpose, function, and syntax of MOTIVE Clock Reference Files, see the MOTIVE System Reference.

16. Choose the Edit (Simple clock reference generation) tab. Specify the names for the Clock reference and Clock net name options. Choose Generate.

17. Choose the Check (Choose incremental definitions) tab, then choose the Load Clock button.

18. Choose Finish from the vertical menubar, then choose the Build button. The MOTIVE Interaction Log & Tips dialog displays the current status. Choose OK after a successful completion.

19. Select Save from the File menu in the Setup Advisor.

20. In the MOTIVE Session Log window, choose Verify (Analyze menu) and then choose the Execute button to start verification. To view the output files, choose Output Files (View menu).

Alternatively, you can run MOTIVE analysis on the command line by following these steps:

1. Type the following commands at the UNIX prompt:

   `vtran` <project name>`.vo -b -h -u alt_max2.vo` (generates .pin files)

   `sdf2mtv` <project name>`.sdfo` (generates .ctl files)

2. If your project contains `ram`, `rom`, `dpram`, or `clklock` functions, you should also type the following commands at the UNIX prompt:

   `genmtv -v` <project name>

   `mmp` <project name>`.ctl -l /usr/maxplus2/Viewlogic/library/alt_time/motive.lib -l /usr/maxplus2/Viewlogic/library/alt_time/motive/drv -l mem.lib`

3. Type the following command at the UNIX prompt: `amtv` <project name>

## Viewlogic Powerview Graphical User Interface & the Altera Toolbox

You use the Powerview graphical interface manager, the Cockpit, and the Altera® Toolbox to start all Powerview and Altera tools. Within the Altera Toolbox, you can specify the Max2 Express Drawer or the Design Tools Drawer to work with the Altera/Viewlogic Powerview interface.

The Max2 Express Drawer provides a quick and seamless way to transfer designs created in Powerview to the MAX+PLUS® II software for compilation, then return the compiled designs to Powerview for simulation and timing verification. Table 1 describes the Max2 Express Drawer tools.

#### Table 1. Max2 Express Drawer Tools

Tool | Description
--- | ---
max2_VDraw | Launches the Powerview ViewDraw schematic entry tool.
VHDL<->max2 | Launches all tools necessary to synthesize a VHDL design, compile for an Altera device, and generate a .vsm file for simulation with the Powerview ViewSim simulator.
SCH<->max2 | Launches all tools necessary to compile a schematic design entered with Powerview ViewDraw software for an Altera device and to generate a .vsm file for simulation with Powerview ViewSim and .edo, .sdo, and .vmo files for timing analysis with MOTIVE for Powerview.
max2_VSim | Launches the Powerview ViewSim simulator.
max2_VTrace | Launches the Powerview ViewTrace simulation waveform editor.
max2_MOTIVE | Launches the MOTIVE for Powerview ViewDraw static timing verification tool.

The Design Tools Drawer provides tools that enable you to create a design with the Powerview tools, compile the design in the MAX+PLUS II software, and simulate and verify the design with Powerview software. Table 2 describes the Design Tools Drawer tools.

#### Table 2. Design Tools Drawer Tools

Tool | Description
--- | ---
max2_VDraw | Launches the Powerview ViewDraw schematic entry tool.
max2_analyzer | Launches the Powerview VHDL Analyzer software.
max2_syn | Launches the Powerview VHDL synthesis tool.
max2_chk | Launches the Powerview schematic verification tool.
max2_vsmnet | Launches the Powerview vsm utility that converts a wirelist file into a .vsm file.
max2_VSim | Launches the Powerview ViewSim simulator.
max2_VTrace | Launches the Powerview ViewTrace simulator.
max2_edifo | Launches the Powerview EDIF netlist writer, edifneto.
max2_VGen | Launches the Powerview ViewGen utility that generates a schematic from a wirelist file.
max2 | Launches the MAX+PLUS II Compiler.
max2_edifi | Launches the Powerview EDIF Netlist Reader, edifneti.
max2_vhdl2sym | Launches the Powerview vhdl2sym utility that generates a symbol from a VHDL file.
max2_VantgMgr | Launches the Powerview Vantage VHDL Library Manager tool.
max2_VantgAnlz | Launches the Vantage VHDL Analyzer software.
max2_VCS | Launches the Fusion/VCS Simulator.
max2_MOTIVE | Launches the MOTIVE for Powerview static timing verification tool.

## Powerview Command-Line Syntax

Table 1 shows the command-line syntax for using Powerview functions.

#### Table 1. Powerview Command-Line Syntax

Action | Command
--- | ---
Start VHDL Analyzer software | `vhdl -v` <project name>
Start ViewSynthesis software | `vhdldes`
Load Altera® technology library | `vhdldes> technology altera`
Compile a VHDL design | `vhdldes> vhdl` <project name>
Synthesize a design | `vhdldes> synthesize`
Generate wirelist file | `vhdldes> wir`
Create a schematic representation | `vhdldes> viewgen`
Generate a synthesis report file | `vhdldes> report`
Start the graphical user interface for ViewSynthesis | `vhdldes> vdesgui`
Start the VHDL-to-symbol utility | `vhdl2sym` <project name>
Start vsm | `vsm` <project name>
Start ViewSim simulator | `viewsim` <project name> -<project name>`.cmd`
Start edifneto | `edifneto -f` <project name>-`l` (`std` or `altera`) <project name>`.edf`
Start Vantage VHDL Analyzer software | `analyze -src` <design file>
Start MOTIVE for Powerview software | `mfp`

## Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

| Refer to the following sources for additional information:

- Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

- Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   | Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   | You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type `setacf -h` and `maxplus2 -h` for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      | If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than `VCC` or `GND` for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   - Exemplar Logic Galileo Extreme-Specific Compiler Settings
   - Synopsys DesignWare-Specific Compiler Settings
   - Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   - Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      | This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   | See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

- JEDEC Files (.jed)
- Programmer Object Files (.pof)
- SRAM Object Files (.sof)
- Hexadecimal (Intel-format) Files (.hex)
- Tabular Text Files (.ttf)

| Refer to the following sources for additional information:

- Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
- Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
- Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware

## Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS® II software, you can program an Altera® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

#### Figure 1. MAX+PLUS II Device Programming Flow

| Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

##### Table 1. Altera Programming Hardware

Programming Hardware Option | PCs | UNIX Work- stations | ACEX® 1K Devices | MAX® 3000A Devices | Classic® & MAX 5000 Devices | MAX 7000 & MAX 7000E Devices | MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000
&
MAX 9000A
Devices

FLEX® 6000,
FLEX 6000A,
FLEX 8000,
FLEX 10K,
FLEX 10KA,
FLEX 10KB,
&
FLEX 10KE Devices
In-System
Programming/
Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and
device-specific
adapters
BitBlaster™ Download Cable |  |  |  |  |  |  |  |  |
ByteBlasterMV™ Download Cable |  |  |  |  |  |  |  |  |
MasterBlaster™ Download Cable |  |  |  |  |  |  |  |  |

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

| Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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