## Instantiating the clklock Megafunction in Concept Schematics

You can instantiate the `clklock` phase-locked loop megafunction, which is supported in selected FLEX® 10K devices, in a Concept schematic. that employ a phase-locked loop (PLL).

To instantiate the `clklock` megafunction in Cadence Concept schematics, follow these steps:

1. Choose the Add Part button from the toolbar or type `add` in the Concept window to open the Component Browser window.

2. Enter the `clklock` megafunction:

   1. Choose alt_max2 (Library menu) and select clklock from the list box.

   2. Type `attribute`, then select the `clklock` component. Change the CLOCKBOOST and INPUT_FREQUENCY values as needed. For detailed information on the `clklock` megafunction, choose Megafunctions/LPM from the MAX+PLUS® II Help menu.

3. Choose Done.

4. Continue with the steps necessary to complete your Concept schematic, as described in Creating Concept Schematics for Use with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept schematic file, which includes `clklock` instantiation:

- /usr/maxplus2/examples/cadence/example12/fifo

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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