## Using Cadence Synergy & MAX+PLUS II Software

The following topics describe how to use the Cadence Synergy software with MAX+PLUS® II software. Click on one of the following topics for information:

CLICK HERE to open a printable version of all topics listed on this page.

### Setting Up the MAX+PLUS II/Cadence Working Environment

- Software Requirements
- MAX+PLUS II/Cadence Interface File Organization
- Altera-Provided Logic & Symbol Libraries

### Design Entry

- #### Design Entry Flow

- #### Creating VHDL Projects

  - Creating VHDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
  - Entering Resource Assignments
    - Modifying the Assignment & Configuration File with the setacf Utility

- #### Creating Verilog HDL Projects

  - Creating Verilog HDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
  - Entering Resource Assignments
    - Modifying the Assignment & Configuration File with the setacf Utility

### Synthesis & Optimization

- #### VHDL

  - Synthesizing & Optimizing VHDL Files with Synergy Software
  - Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility

- #### Verilog HDL

  - Synthesizing & Optimizing Verilog HDL Files with Synergy Software
  - Converting Verilog HDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt Utility

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Programming Altera Devices

| Go to the following topics , which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Cadence web site (http://www.cadence.com)

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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