## Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software

You can perform a functional simulation of a Concept schematic with the hdlconfig utility and Verilog-XL software before compiling your project with the MAX+PLUS® II software.

To functionally simulate a Concept schematic, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Create a Concept schematic and save it in your working directory, as described in Creating Concept Schematics for Use with MAX+PLUS II Software.

3. Use the hdlconfig utility to create a Verilog HDL text file that contains the entire design. Type the following command at the UNIX prompt from the /<working directory>/<design name>/source directory:

   `hdlconfig -a -c -r` <design name>`-o` <design name>`.v logic verilog_lib`

4. If your design contains RAM or ROM functions (e.g., `lpm_ram_dq`, `lpm_ram_io`, `lpm_rom`, `scfifo`, `dcfifo`, `altdpram`, and `csdpram`), run the vconfig utility to link the object convert_hex2ver.o to build a new Verilog-XL file that supports these functions by following these steps:

   1. Create a copy of the Verilog executable file by typing the following command at the UNIX prompt:

      `cp -p $CDS_INST_DIR/tools/verilog/bin/verilog $CDS_INST_DIR/tools /verilog/bin/ verilog.bak.`

   2. Type `vconfig` at the UNIX prompt from the /usr/maxplus2/cadence/bin directory to start the script.

   3. Accept `cr_vlog` as the name of the output script.

   4. Accept `1` as the stand-alone target.

   5. Type `new_verilog` as the name for the Verilog-XL target.

   6. Respond `Yes` when you are prompted to compile for the Verilog-XL environment.

   7. Respond `No` when you are prompted to include the Dynamic LAI, STATIC LOGIC AUTOMATION, LMSI HARDWARE MODELER, Verilog Mixed-Signal, and CDC interfaces in this executable.

   8. Respond `Yes` when you are prompted to include the Standard Delay File Annotator (SDF).

   9. Specify /usr/maxplus2/verilog/veriuser.c when you are asked the name of the user template file. For more information about the contents of the veriuser.c file, you can refer to the veriuser.doc file, which is available in the Cadence Openbook product documentation. To locate this document, start Openbook, and choose Alphabetical List of Products from the main menu. Scroll through the pages until you locate the PLI 1.0 User Guide & Reference in the PLI section, and then continue to scroll through the document until you locate the veriuser.doc file under "Section A" and "PLI Code Examples."

   10. When you are asked the name of files to be linked with the Verilog-XL simulator, specify the hexadecimal (Intel-format) conversion file /usr/maxplus2/cadence/share/verilog/convert_hex2ver.o, followed by a single period (`.`).

   11. Run the output script cr_vlog to build the new Verilog-XL executable in the /usr/maxplus2/cadence/bin directory. Make sure that the `$CDS_INST_DIR/tools/bin` path appears at the beginning of the `PATH` statement in the .cshrc file.

   12. If your C language library installation is different from the default location /usr/lang/SC3.0.1, type the following command at the UNIX prompt:

       `setenv C_DIR` <C language library installation directory>

   13. If successful, replace the old Verilog executable file with the new one by typing the following command at the UNIX prompt:

       `cp -p new_verilog $CDS_INST_DIR/tools/verilog/bin/verilog`

5. Generate the stimulus file for the design and start the Verilog-XL simulator by typing the following command at the UNIX prompt from the /<working directory>/<design name>/source directory:

   `verilog -y /usr/maxplus2/simlib/concept/alt_max2/verilogUdps +libext+.v+.V` <stimulus file name> <design name>`.v`

6. When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the concept2alt utility, as described in Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt Utility.

7. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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