## Assigning Logic Options

Logic options and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS® II Compiler also uses a device family-specific default logic synthesis style for each project.

To make pin, logic cell, and chip assignments, use the `set_attribute` command at a dc_shell prompt. Before using the `set_attribute` command, add the following line to your .synopsys_dc.setup file:

`edifout_write_properties_list` = {`LOGIC_OPTION, CLIQUE, CHIP_PIN_LC`}

| To assign a logic option or a logic synthesis style, type the following command at a dc_shell prompt:
| `set_attribute find(`<design object>`, (`<instance name>`)) "LOGIC_OPTION" -type string "`<logic option>`=`<value>`"`
| For example:
| `set_attribute find (cell, (U1)) "LOGIC_OPTION" -type string "STYLE=FAST"`
| To specify multiple logic options, use commas as separators.
| For example:
| `set_attribute find (cell, (U1))"LOGIC_OPTION" -type string "STYLE=FAST, CARRY_CHAIN=MANUAL"`

|  | Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Design Compiler & FPGA Compiler Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.