## Running Synopsys Compilers from the MAX+PLUS II Software

With MAX+PLUS® II software, you can automatically process Verilog HDL and VHDL designs with the Synopsys Design Compiler or FPGA Compiler by following these steps:

1. Create a project directory under your login directory.

2. Add the following environment variables to your .cshrc file:

   `setenv ALT_HOME /`<MAX+PLUS II system directory> `setenv SYNOPSYS /`<Synopsys system directory>

3. Add the $ALT_HOME/synopsys/bin and $SYNOPSYS/$ARCH/syn/bin directories to the PATH environment variable in your .cshrc file. The $ARCH environment variable specifies the platform on which the Synopsys Design Compiler is running. Valid platform names are `sparc`, `sparcOS5`, `rs6000`, and `hp700`.

4. Source your .cshrc file to update the environment variables.

   | If you use additional custom libraries, you must specify them in a .synopsys_dc.setup file, and verify that it contains the correct library settings for mapping to the target family. See Setting Up the Synopsys/MAX+PLUS II Working Environment for more information about the .synopsys_dc.setup file.

5. Create your project in Verilog HDL or VHDL using the MAX+PLUS II Text Editor or another standard text editor. You must save Verilog HDL files with the extension .v and VHDL files with the extension .vhd.

   | If you use the MAX+PLUS II Text Editor to create your design, you can insert templates for Verilog HDL or VHDL constructs with the Verilog Template and VHDL Template commands (Templates menu). The MAX+PLUS II Text Editor also provides syntax coloring for Verilog HDL and VHDL files to improve file readability.

6. In the MAX+PLUS II software, specify the project to be compiled with Project Name (File menu). Make sure the project name specified in MAX+PLUS II software matches both the name of the top-level design file and the Entity Declaration name specified in the top-level design file.

7. Click Button 1 on the Compiler toolbar button or choose the Compiler command (MAX+PLUS II menu) to open the Compiler.

8. In the MAX+PLUS II Compiler, turn on the Synopsys Compiler command (Interfaces menu).

9. Open the Synopsys Compiler Settings dialog box by choosing Synopsys Compiler Settings (Interfaces menu). Specify the appropriate options:

   1. Select either Design Compiler or FPGA Compiler in the Compiler box to specify which Synopsys compiler you want to process the design.

   2. If you wish to use the DesignWare interface and libraries, turn on the DesignWare (FLEX® devices only) option (FLEX 6000, FLEX 8000, and FLEX 10K devices only).

   3. To preserve the design hierarchy during Synopsys compilation, turn on the Hierarchical Compilation option. Turning off this option allows the Synopsys compiler to flatten the design.

   4. To allow the Synopsys compiler to optimize across all hierarchical boundaries, turn on the Boundary Optimization option.

   5. Select the Low, Medium, or High option for Mapping Effort.

   6. Choose OK to save all changes.

10. If you have turned on the DesignWare (FLEX devices only) option in the Synopsys Compiler Settings dialog box, ensure that the global project synthesis style uses the correct settings. Refer Compiling Projects with MAX+PLUS II Software for more information.

11. Specify the device(s) and output file(s) for the project. If you do not specify a device, the MAX+PLUS II Compiler automatically selects one or more devices from the current device family. Refer to Creating VHDL Design Files for Use with MAX+PLUS II Software for more information.

12. Choose the Start button to compile the project. The MAX+PLUS II software converts the EDIF Input File, flattens the project, fits it into one or more Altera® devices, and generates the selected output files, including programming files. The MAX+PLUS II Message Processor notifies you when one of the Synopsys compilers is processing your design. When it has finished processing the design file(s), the Synopsys compiler generates an EDIF netlist file for each design in the hierarchy, and the MAX+PLUS II software immediately compiles the EDIF Input File(s).

Altera provides the mp2dc_ana and mp2dc_cmp shell scripts, which specify Synopsys Design Compiler or FPGA Compiler settings automatically. These scripts read the settings you have specified in the Device (Assign menu) and Synopsys Compiler Settings (Interfaces menu) dialog boxes for the project device(s), search path, link library, target library, synthetic library options (if you have turned on the DesignWare option in the Synopsys Compiler Settings dialog box), and other optimization options. You do not need to provide your own .synopsys_dc.setup file unless you use libraries other than Altera libraries. See Setting Up Synopsys Configuration Files for more information.

The MAX+PLUS II software runs both the mp2dc_ana and mp2dc_cmp shell scripts automatically when you compile a VHDL or Verilog HDL design file with the Synopsys Compiler command (Interfaces menu) turned on. The mp2dc_ana shell script analyzes your designs and generates a single hierarchical .db database file. The analysis output information is recorded in the <project name>.log file. If the Design Compiler or FPGA Compiler generates errors or warning messages during processing, the messages appear in the MAX+PLUS II Message Processor window. You can select a message that includes a line number and click Button 1 on the Locate button to locate the source of a message in the MAX+PLUS II Text Editor. If no errors occur during analysis, the MAX+PLUS II software then starts the mp2dc_cmp shell script to read the .db file, compile the design, and generate an EDIF netlist file for each design file in the hierarchy, which the MAX+PLUS II software then processes as an EDIF Input File (.edf).

The the mp2dc_ana and mp2dc_cmp shell scripts are located in the /usr/maxplus2/synopsys/bin directory. You can copy the mp2dc_cmp shell script to your project directory and specify custom settings for your design, such as Clock frequency or timing constraints settings. Alternatively, you can create your own custom dc_shell script and name the file my_mp2dc.scr. The mp2dc_cmp shell script will then use the commands in the my_mp2dc.scr file and ignore the current settings or default settings for Synopsys compilation options. Figure 1 shows an excerpt of the Altera-provided mp2dc_cmp shell script.

Figure 1. Excerpt from Altera-Provided mp2dc_cmp Shell Script

    read -f db $proj.db >> $proj.log
       if (dc_shell_status == {}) {
       quit
       }
    current_design=$design
    uniquify
    set_max_area 0
    designs= find(design, "*")
    foreach (dsgn, designs) {
            current_design= dsgn
            edfout_file = ""
            edfout_file = dsgn
            edfout_file = edfout_file + ".edf"
            set_max_area 0
    /* If you do not use my_mp2dc.scr to customize your compilation, the */
    /* customizable settings in the following section are used. You can  */
    /* customize these settings only if the mp2dc_cmp file is located in */
    /* your project directory.                                           */

       if ( "$use_my_cmd" == "true") {
          include my_mp2dc.scr
       } else {
       /* if no hierarchical compilation, then flatten the design  */
          if ( "$hierarchical_compile" == "OFF") {
                set_structure false
                set_flatten -effort low
                ungroup -all
          }
          /* test compile options */
          if ( "$boundary_opt" == "ON") {
                compile -boundary_optimization -map_effort $map_effort
          } else {
               compile  -map_effort $map_effort
          }
          /* If you use FPGA Compiler for FLEX devices, the LUT equation is output.*/
          /* If you use Design Compiler for FLEX devices, a TBL cell is output.    */
          if ( ("$family" == "flex8000") || ("$family" == "flex10k") ) {
             if ( "$synopsys_compiler" == "FPGA" ){
                edifout_write_properties_list = {"lut_function"}
             }  else {
                replace_fpga
             }
          }
     }    /* End of customizable compilation settings section */
          write  -f edif current_design  -o edfout_file
          if (dc_shell_status == {}) {
                quit
          }
    }

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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