## Assigning the Implement in EAB Logic Option

You can assign the Implement in EAB logic option to individual logic functions in a FLEX® 10K design. This option directs the MAX+PLUS® II Compiler's Logic Synthesizer module to implement the function in an embedded array block (EAB) rather than in logic cell(s). You can specify the Implement in EAB Logic Option in VHDL or Verilog HDL designs, or in a Synplify Design Constraints File (.sdc). If you add timing constraints or resource assignments in a separate Synplify Design Constraints File (.sdc), you must add the Synplify Design Constraints File (.sdc) to the project by adding it to the Source Files list in the Synplify window.

| If your design uses resource assignment attributes that you wish to pass to the MAX+PLUS II software, you should save your file in EDIF netlist file format. See Entering Resource Assignments for more information.

#### VHDL Syntax

Use the following syntax to assign the Implement in EAB logic option in VHDL:

`attribute altera_implement_in_eab : boolean;`
`attribute altera_implement_in_eab of` <port name>: `label is true;`

Example:

    attribute altera_implement_in_eab of U1: label is true;
        begin
            U1: mymux port map (in1 => a, sel => s, dout => o);

#### Verilog HDL Syntax

Use the following syntax to assign the Implement in EAB logic option in Verilog HDL:

<module or architecture name>`/* synthesis altera_implement_in_eab=1 */;`

Example:

    sqrtb sq (.z(sqa), .a(a))  /* synthesis altera_implement_in_eab=1 */;
    defparam sq.asize = 8;

#### Synplify Design Constraints File Syntax

Use the following syntax to assign the Implement in EAB logic option in a Synplify Design Constraints File (.sdc):

`define_attribute {`<module or architecture name>`} altera_implement_in_eab 1`

Example:

`define_attribute {inst1.sqrt8} altera_implement_in_eab 1`

| Refer to the following sources for more information:

- Go to Entering Resource Assignments in these MAX+PLUS II ACCESSSM Key topics for information on entering other types of assignments.
- Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on other logic options and logic synthesis style assignments, including definitions and syntax of these assignments.

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Synplify Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.