## DesignWare Up/Down Counter Function Instantiation Example for VHDL

The Altera DesignWare Libraries for FLEX devices allow you to instantiate the `DW03_updn_ctr` function, which is the same as the Synopsys `DW03` up/down counter. This function allows you to use the same VHDL code regardless of which FLEX® device is targeted.

Figure 1 shows a VHDL file excerpt with `DW03_updn_ctr` instantiation.

Figure 1. VHDL File Excerpt with Up/Down Counter Instantiation
    LIBRARY ieee,DW03;
    USE ieee.std_logic_1164.all;
    USE DW03.DW03_components.all;
    ENTITY updn_4 IS
       PORT (D : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
          UP_DN, LD, CE, CLK, RST: IN STD_LOGIC;
          TERCNT : OUT STD_LOGIC;
          Q      : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0));
    END updn_4;
    ARCHITECTURE structure OF updn_4 IS
    BEGIN
       u0: DW03_updn_ctr
       GENERIC MAP(width => 4)
       PORT MAP (data => d, clk => clk, reset => rst, up_dn => up_dn,
                 load => ld, tercnt => tercnt, cen => ce, count => q);
    END structure;

| Go to Setting Up the DesignWare Interface in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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