## Exemplar Logic Galileo ExtremeSpecific Compiler Settings

If you are using MAX+PLUS® II software to compile a FLEX® design that was created with Galileo Extreme software, go through the following additional compilation steps:

1. Choose Global Project Logic Synthesis (Assign menu) to open the Global Project Logic Synthesis dialog box.

2. Select the appropriate logic synthesis style under Global Project Logic Synthesis Style:

| If you turned on the Lock Lcells option under SYNTHESIS SWITCHES in the Galileo Extreme Altera FLEX Output Options dialog box when synthesizing your design with Galileo Extreme software, select WYSIWIG in the Global Project Synthesis Style box.

or:

| If you did not turn on the Lock Lcells option, select FAST in the Global Project Synthesis Style box.

3. (Optional) Turning on one or more of the following options may help to improve area usage and timing delays:

- Automatic Fast I/O
- Automatic Register Packing
- (FLEX 10K devices only) Automatic Implement in EAB

4. Choose OK to close the Global Project Logic Synthesis dialog box.

5. Continue with the steps necessary to compile your project, as described in Compiling Projects with MAX+PLUS II Software.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX® Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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