## Instantiating the clklock Megafunction in Design Architect Schematics

You can instantiate the Altera®provided `clklock` phase-locked loop megafunction, which is supported for some FLEX® 10K devices, in a Design Architect schematic.

To instantiate the `clklock` megafunction in a Design Architect schematic, follow these steps:

1. Choose Altera Libraries (Library menu).

2. Choose ALTERA GENLIB (Altera Libraries menu).

3. Choose clklock (ALTERA GENLIB menu).

4. Specify appropriate values for the `CLOCKBOOST` and `INPUT_FREQUENCY` variables. Choose Megafunctions/LPM from the MAX+PLUS® II Help menu for detailed information on the `clklock` megafunction.

5. Choose OK.

6. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example7/fifo, which includes `clklock` megafunction instantiation.

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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