## Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints

You can assign pins, logic options, or timing constraints to your design in FPGA Express constraint tables. Some design-specific information is extracted automatically from your design and displayed in the constraint tables; you can also manually enter specific assignments in these tables. The FPGA Express software saves the assignments to an Assignment & Configuration File (.acf) when it synthesizes and optimizes the design. The MAX+PLUS® II software uses the assignment information from the ACF when it processes the design. Refer to Using ACFs Generated by FPGA Express Software for more information.

To enter resource assignments in FPGA Express software, follow these steps:

1. Select the design implementation icon in the Chips window, press Button 2, and choose the Edit Constraints commmand from the pop-up menu to display the Altera-specific constraint tables. These tables allow you to specify resource assignments for your design. All design-specific information such as Clock names, port names, and design hierarchy is extracted automatically from the design. Altera recommends entering specific requirements directly into these tables to obtain the desired optimization. For information on creating a design implementation, refer to steps 1 through 8 in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

2. Enter assignments in the appropriate constraint tables. You can click on a tab to toggle between tables. Refer to Table 1, which shows the available MAX+PLUS II resource assignment options in the FPGA Express constraint tables. The Clock and Path tables already contain information that you previously entered in the Create Implementation dialog box. Refer to Assigning a Device & Clock Frequency (fMAX) for more information.

   Table 1. MAX+PLUS II Resource Assignments in FPGA Express Constraint Tables

   MAX+PLUS II Resource Assignment | Equivalent FPGA Express Constraint Table Setting
   Tab Name | Action
   Pin assignment | Ports | Specify the pin number in the Pad Location column.
   tSU timing assignment | Ports | Specify the time in the Input Delay column.
   tCO timing assignment | Ports | Specify the time in the Output Delay column.
   Slow Slew Rate logic option assignment | Ports | Click on the appropriate cell in the Slew Rate column and select <default>, FAST, or SLOW from the list.
   Fast I/O logic option assignment | Ports | Click on the appropriate cell in the Use I/O Reg column and select <default>, ON, or OFF from the list.
   tPD timing assignment | Paths | Specify the time in the Delay column.

3. Choose Save and then Close to exit from the FPGA Express constraint tables.

| Go to the following sources for related information:

- FPGA Express Help
- "Guidelines for Achieving Maximum Speed Performance" in MAX+PLUS II Help
- Specifying the MAX+PLUS II Logic Synthesis Style with the FPGA Express Software in these MAX+PLUS II ACCESSSM Key topics

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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