## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software

After you have created a VHDL or Verilog HDL design, you can use Exemplar Logic's Galileo Extreme software to synthesize and optimize your VHDL Design File (.vhd) or Verilog Design File (.v) and prepare it for compilation with the MAX+PLUS® II Compiler.

To synthesize and optimize your project and generate an EDIF netlist file with Galileo Extreme software, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software.

4. Select the icon for your design file in the appropriate directory, press Button 3, and choose max2_galileo in the Navigator window to start the Galileo Extreme software. You can also start Galileo Extreme software by typing `max2_galileo` at the UNIX prompt.

5. Specify settings for the Filename and Format options under INPUT DESIGN.

6. Specify settings for the Filename, Format, and Technology options under OUTPUT DESIGN. Verify that EDIF is specified in the Format box.

7. Choose the Altera Output Options button if you want to specify settings for various parameters, including Maximum Fanin for MAX devices and Part Number for FLEX devices. You can also turn on the Run MAX+PLUS II option for design compilation, which specifies that the MAX+PLUS II Compiler should start processing your design immediately after you run Galileo Extreme. Choose OK to save any setting changes.

8. Choose Start Run. The Galileo Extreme software generates <design name>.edf in the <project directory>/max2 subdirectory and then closes, returning you to the Navigator window.

9. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. If you turned on the Run MAX+PLUS II option in step 7, the MAX+PLUS II Compiler automatically starts processing your design after you run Galileo Extreme.

Installing the Altera®provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL Design Files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software
- Performing a Timing Simulation with QuickHDL Software
- Performing a Timing Analysis with QuickPath Software

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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