## Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000 & FLEX 10K Devices

The Synopsys FPGA Compiler software supports an N-input look-up table (LUT) function that improves the quality of the results and the predictability of delay and resource estimates. All Altera® FPGA Compiler libraries for FLEX® 6000, FLEX 8000, and FLEX 10K devices support the N-input LUT function.

Figure 1 shows a sample command sequence that FPGA Compiler might require for N-input LUT optimization. To use N-input LUT optimization, include the `edifout_write_properties_list = "lut_function"` command.

Figure 1. Sample Command Sequence for N-Input LUT Optimization
`read -f vhdl` <design name>`.vhd` `current_design =` <design name>`` `set_max_area 0` `uniquify` `ungroup -all -flatten`
`compile -ungroup_all`
`report_area >` <design name>`.rpa`
`report_fpga >` <design name>`.rpf`
`report_cell >` <design name>`.rpc`
`edifout_write_properties_list = "lut_function"`
`write -f edif -hierarchy -o` <design name>`.edf`

Use the area report to determine the circuit area.

If you wish to maintain area report estimates as closely as possible during MAX+PLUS® II processing, Altera recommends that you select the WYSIWYG setting for the Global Project Synthesis Style in the Global Project Logic Synthesis dialog box (Assign menu). However, selecting the Normal or Fast style may yield a better result.

| For more information on how to use the FPGA Compiler software optimize your design for FLEX 8000 devices, refer to Chapter 5: Optimization for the Altera FLEX 8000 Architecture in the Synopsys FPGA Compiler User Guide.

| Go to FLEX Devices, which is available on the web, for additional information:

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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