## Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for you project. The MAX+PLUS II Text Editor offers the following advantages:

- Verilog HDL templates are available with the Verilog Templates command (Templates menu). These templates are also available in the ASCII verilog.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your Verilog HDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a Verilog HDL design that can be synthesized and optimized with Synergy software, go through the following steps:

1. You can instantiate the following MAX+PLUS II-provided logic functions in your Verilog HDL design:

   - The alt_max2 library, which contains the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` macrofunctions that are optimized for different Altera device families.

   - The `clklock` megafunction which enables phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the `clklock` Megafunction in VHDL or Verilog HDL for information.

   - The lpm_syn library, which contains the Cadence LPM megafunction library for use with Synergy Software and Concept or Composer software.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. You can enter resource assignments in your Verilog HDL design, as described in Entering Resource Assignments.

3. After you have completed your Verilog HDL design, synthesize and optimize it with Synergy software, as described in Synthesizing & Optimizing Verilog HDL Files with Synergy Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files, the latter of which includes LPM function instantiation.

- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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