## Performing a Timing Simulation with Leapfrog Software

Once the MAX+PLUS® II software has compiled a project and generated a VHDL Output File (.vho), you can a perform timing simulation using Cadence Leapfrog software.

To simulate a VHDL output file with the Leapfrog timing simulator, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. If you wish to use MAX+PLUS II-generated Standard Delay Format (SDF) Output Files (.sdo) that contain timing information, compile the VITAL library source files, as described in Compiling the VITAL Library for Use with Leapfrog Software.

3. If your design uses functions from the alt_mf library, compile the library, as described in Compiling the alt_mf Library.

4. Generate a VHDL Output File (.vho) and an optional SDF Output File, as described in Compiling Projects with MAX+PLUS II Software.

5. Using any standard text editor, create a stimulus file that includes test vectors for <design name>.

6. Start the Leapfrog simulator and simulate the MAX+PLUS II-created VHDL Output File <design name>.vho by typing `leapfrog` at the UNIX prompt. Refer to Chapter 5: SDF Back-Annotation in Leapfrog in the VHDL Simulator User Guide or refer to the Cadence Openbook for more information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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