## Performing a Timing Simulation with Verilog-XL Software

Once the MAX+PLUS® II software has compiled a project and generated a Verilog Output File (.vo), you can perform a timing simulation using Cadence Verilog-XL software.

To simulate Verilog output files with the Verilog-XL timing simulator, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Generate Verilog Output Files (.vo), as described in Compiling Projects with MAX+PLUS II Software. The MAX+PLUS II Compiler generates the <design name>.vo and alt_max2.vo files for use with Verilog-XL software.

3. Using any standard text editor, create a stimulus file that includes test vectors for your design.

4. Start the Verilog-XL simulator and simulate your Verilog output files by typing the following command at the UNIX prompt:

   `verilog` <stimulus filename(s)> <design name> `alt_max2.vo`

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Cadence Topics | Verilog-XL Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.