## Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- Verilog HDL templates are available with the Verilog Templates command (Templates menu). These templates are also available in the ASCII verilog.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your Verilog HDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a Verilog HDL design and convert it to an EDIF netlist file for use with MAX+PLUS II software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synplicity Working Environment.

2. Instantiate any MAX+PLUS II-supported logic function in your Verilog HDL design. You can enter the following functions:

   - Parameterized and non-parameterized megafunctions. MAX+PLUS II software also supports all functions in the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions.

   - Macrofunctions, including 74-series functions.

   - Buffer primitives, including `lcell`, `soft`, `global`, `carry`, and `cascade`. The Synplicity altera.v library provides synthesis support for these functions.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

   Choose Primitives, Old-Style Macrofunctions, and Megafunctions/LPM from the MAX+PLUS II Help menu for information on all MAX+PLUS II-supported functions.

3. If your design uses functions from the altera.v library, add the library file name to the top of the Source Files list in the Synplify window.

4. For each MAX+PLUS II-supported logic function, include a `black_box` synthesis directive. You can omit this step for functions from the altera.v library.

5. For any parameterized function, you must declare all parameters used in the function, and their values. Figure 1 shows a Verilog HDL file that instantiates the `lpm_ram_dq` function. A comment in the Module Declaration contains the `synthesis black_box` directive and parameter names and values. This comment must immediately follow the port list and precede the closing semicolon (`;`). When you instantiate an LPM function, the LPM function name must be specified as the value of the `LPM_TYPE` parameter. In addition, each parameter must be listed on a separate line. See Figure 1.

   #### Figure 1. Verilog HDL Design File with LPM Function Instantiation

       // Define the black box
       module myram_64x16 (data, address, inclock, outclock, we, q)
       /* synthesis black_box

                          LPM_WIDTH=16
                          LPM_WIDTHAD=6
                          LPM_TYPE="LPM_RAM_DQ"  */ ;

       input [15:0] data;
       input [5:0] address;
       input inclock, outclock;
       input we;
       output [15:0] q;

       endmodule

       // Instantiate the LPM parameterized module in the
       //    higher-level module myram
       module myram(clock, we, data, address, q);
       input clock, we;
       input [15:0] data;
       input [5:0] address;
       output [15:0] q;

              myram_64x16 inst1 (data, address, clock, clock, we, q);

       endmodule

6. (Optional) Enter resource assignments for your Verilog HDL design, as described in Entering Resource Assignments.

7. After you have completed your Verilog HDL design, synthesize and optimize it with Synplify software, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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