## Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software

You can analyze, synthesize, and optimize design files using the FPGA Express software, then convert them to EDIF netlist files that can be processed by the MAX+PLUS® II software.

To process a VHDL or Verilog HDL design for use with MAX+PLUS II software, follow these steps:

1. Create a VHDL file, <design name>.vhd, or Verilog HDL file, <design name>.v, using the MAX+PLUS II Text Editor or another standard text editor and save it in your working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software or Creating Verilog HDL Designs for Use with MAX+PLUS II Software for more information on VHDL or Verilog HDL design entry.

2. Start the FPGA Express software. Select Create a new project in the Startup dialog box and choose OK. The Create Project Folder dialog box is displayed. You can also view the Create Project Folder dialog box by choosing New (File menu).

3. Specify the full file and path name of the project in the Create Project Folder dialog box and choose Create. The FPGA Express software creates the project and opens the Identify Source File dialog box.

4. Identify and analyze the source files for the project by selecting them in the Identify Source File dialog box and choosing Add. The FPGA Express internal text editor automatically analyzes each source file as it appears on the left-hand side of the Project window. A green checkmark appears to the left of each filename for the files that have no errors or warnings; a red cross appears for files with errors; and an exclamation point appears for files with warnings.

5. Select the source file icon to display any errors or warnings in the Output window. To fix an error, double-click on the error. The FPGA Express internal text editor automatically displays the source file and highlights the line containing the error or warning in red. To view help on the error or warning, double-click on the error or warning code number (shown in parentheses) in the Output window.

   | FPGA Express software does not copy source files; it identifies and analyzes them in their current location. Refer to FPGA Express Help for more information.

6. Specify the MAX+PLUS II logic synthesis style. Refer to Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express software for more information.

7. From the Project window, identify the top-level design for your project. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.

8. In the Create Implementation dialog box, specify the following options:

   1. Assign a device and the Clock frequency. Refer to Assigning a Device & Clock Frequency (fMAX) for more information.

   2. Select a global optimization goal (speed or area) and a CPU effort designation (high or low). Refer to Specifying the Speed/Area & CPU Effort Settings with the FPGA Express Software for information.

   3. Close the Create Implementation dialog box by choosing OK.

   The FPGA Express software processes each source file and determines the complete hierarchical structure and topology of the design, including multi-level links and references between subdesigns. With this information, the FPGA Express software produces an intermediate, unoptimized design implementation. The right-hand side of the Project window displays the implementation name and target device. The implementation icon also indicates any errors, warnings, or other information. To correct error or warning conditions, refer to step 5.

9. (Optional) Select the design implementation icon in the Chips window, press Button 2, and choose the Edit Constraints command from the pop-up menu to display the Altera-specific constraint tables. These constraint tables allow you to specify pin, logic option, and timing assignments for your design. All design-specific information, such as Clock names, port names, and design hierarchy assignments is extracted automatically from the design. Altera recommends entering specific requirements directly into these tables to obtain the desired optimization. Refer to Entering Resource, Device & Global Logic Synthesis Assignments for information.

10. Optimize the design by selecting the design implementation in the Project window and choosing the Optimize button on the toolbar. A new optimized implementation icon appears beneath the original implementation icon. When you open the optimized implementation, the constraint tables are back-annotated with the optimization results. The FPGA Express software optimizes a design for either speed or area, based on the settings you specified in step 8.

11. Identify and optimize critical paths in your design with the Time Tracker static timing analyzer, as described in Analyzing Estimated Timing with the FPGA Express Time Tracker.

12. Generate a project report by selecting the optimized design implementation and clicking the Report icon on the toolbar. An FPGA Express project report documents the design through the synthesis and optimization design flow. The report includes information about design source data, constraints, and optimization options.

13. Generate MAX+PLUS II-compatible EDIF netlist files by selecting the optimized design implementation and choosing the Export Netlist button on the toolbar. In the Export dialog box, specify the following options:

    1. Specify the name and location of the directory for the EDIF netlist files in the Export Directory box.

    2. Select the EDIF netlist file's output bus from the Bus Style drop-down list. The MAX+PLUS II software accepts either flattened or unflattened buses. In the FPGA Express software, the default setting, EXPAND, flattens each bus by writing each bus bit as an individual I/O port. To export an EDIF netlist file without flattening the bus names, select any of the other settings, which include delimiters for different bus notations:`[]`, `<>`, `()`, and `{}`.

    3. If you wish to generate a VHDL or Verilog HDL netlist file for functional simulation prior to MAX+PLUS II compilation, select a language option (VHDL or Verilog) from the Output Format drop-down list. Otherwise, select NONE for this option instead.

    4. Turn on the Export Primitives option to export VHDL or Verilog HDL primitives into the simulation netlist file. However, if the simulation is to be performed with an external library, turn the option off.

    5. Close the Export dialog box by choosing OK. The FPGA Express software creates the following MAX+PLUS II-compatible files:

       - <design name>.edf (EDIF format)
       - <design name>.acf, an Assignment & Configuration File that contains design constraints
       - <design name>.lmf, a Library Mapping File that maps FPGA Express functions to MAX+PLUS II functions

14. Copy all three types of output files (EDIF netlist file(s), ACF, and LMF) to a MAX+PLUS II project directory. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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