// MAX+plus II Verilog Example
// User-Defined Macrofunction
// Copyright (c) 1997 Altera Corporation

module reg12 ( d, clk, q);

input [11:0]d;
input clk;
output [11:0]q;

reg [11:0]q;

always @(posedge clk)
     q = d;

endmodule

