## Using Synopsys Design Compiler or FPGA Compiler & MAX+PLUS II Software

The following topics describe how to use the Synopsys Design Compiler and FPGA Compiler software with the MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Synopsys Working Environment

- Software Requirements
- Setting Up Design Compiler & FPGA Compiler Configuration Files
- Setting Up the DesignWare Interface
  - Updating DesignWare Libraries
- Libraries
  - Design Compiler & FPGA Compiler Technology Libraries
  - VHDL & Verilog HDL alt_mf Logic Function Library
  - DesignWare FLEX 6000, FLEX 8000 & FLEX 10K Synthetic Libraries
  - Post-Synthesis Libraries
- MAX+PLUS II/Synopsys Interface File Organization
- MAX+PLUS II Project File Structure

### Design Entry

- #### Design Entry Flow

- #### VHDL

  - Creating VHDL Designs for Use with MAX+PLUS II Software
    - Instantiating RAM & ROM Functions in VHDL (includes examples)
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL (includes examples)
  - Additional examples:
    - Primitive & Old-Style Macrofunction Instantiation Example for VHDL
    - Architecture Control Logic Function Instantiation Example for VHDL
    - DesignWare Up/Down Counter Function Instantiation Example for VHDL

- #### Verilog HDL

  - Creating Verilog HDL Designs for Use with MAX+PLUS II Software
    - Instantiating RAM or ROM Functions in Verilog HDL (includes examples)
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL (includes examples)
  - Additional examples:
    - Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL
    - Architecture Control Logic Function Instantiation Example for Verilog HDL

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Synopsys Software
  - Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000, or FLEX 10K Devices
- Examples:
  - MAX 7000 & MAX 9000 Synthesis Example
  - DesignWare FLEX 8000 Synthesis Example
- Entering Resource Assignments
  - Assigning Pins, Logic Cells & Chips
  - Assigning Cliques
  - Assigning Logic Options
  - Modifying the Assignment & Configuration File with the setacf utility
  - Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
  - Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities
- Performing a Pre-Routing or Functional Simulation with VSS
- Resynthesizing a Design Using the alt.vtl Library & a MAX+PLUS II SDF Output File

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Programming Altera Devices
- Using Synopsys FPGA Express & MAX+PLUS II Software
- Using Synopsys PrimeTime & MAX+PLUS II Software
- Using Synopsys VSS & MAX+PLUS II Software

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Synopsys web site (http://www.synopsys.com)

## Setting Up the MAX+PLUS II/Synopsys Working Environment

To use the MAX+PLUS® II software with Synopsys software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs by modifying your Synopsys configuration files. The MAX+PLUS II/Synopsys interface is installed automatically when you install the MAX+PLUS II software on your workstation. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Synopsys Interface File Organization for information about the MAX+PLUS II/Synopsys directories that are created during MAX+PLUS II installation.

| The information presented here assumes that you are using C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Synopsys interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Synopsys software versions described in the MAX+PLUS II/Synopsys Software Requirements.

2. Add technology, synthetic, and link library settings to your .synopsys_dc.setup configuration file, as described in Setting Up Design Compiler & FPGA Compiler Configuration Files.

   | To use the DesignWare interface with FLEX® 6000, FLEX 8000, and FLEX 10K devices, follow the steps in Setting Up the DesignWare Interface.

3. Add simulation library settings to your .synopsys_vss.setup file, and analyze the libraries, as described in Setting Up VSS Configuration Files.

4. Add the /usr/maxplus2/bin directory to the `PATH` environment variable in your .cshrc file in order to run the MAX+PLUS II software. (Optional) Change the path in the first line of the perl script files, which are located in the `$ALT_HOME`/synopsys/bin directory to specify the correct path of your local perl executable file.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Synopsys Software Requirements

The following applications are used to generate, process, synthesize, and verify a project with MAX+PLUS® II and Synopsys software:

Synopsys | Altera
--- | ---

version 1998.02: Design Compiler 99.05 FPGA Compiler II 3.5 Design Analyzer (optional) VHDL Compiler
HDL Compiler for Verilog
VHDL System Simulator (VSS) (optional)
PrimeTime version 1998.02-PT2.1(optional)

MAX+PLUS II
version 10.0

Compilation with the Synopsys Design Compiler and FPGA Compiler is available only on Sun SPARCstations running Solaris 2.4 or higher.

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Synopsys applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

## Setting Up Design Compiler & FPGA Compiler Configuration Files

The .synopsys_dc.setup configuration file allows you to set both Design Compiler and FPGA Compiler variables. The compilers read .synopsys_dc.setup files from three directories, in the following order:

1. The Synopsys root directory
2. Your home directory
3. The directory where you start the Design Compiler or FPGA Compiler software

The most recently read configuration file has highest priority. For example, a configuration file in the directory where you start the Design Compiler or FPGA Compiler software has priority over the other configuration files, and a configuration file in the home directory has priority over a configuration file in the root directory.

To set up your configuration files, follow these steps:

1. Add the lines shown in Figure 1 to your .synopsys_dc.setup configuration file. Altera provides a sample .synopsys_dc.setup file in the ./synopsys/config directory. Figure 1 shows an excerpt from that sample file.

   Figure 1. Excerpt from Sample .synopsys_dc.setup File
   `search_path = {./usr/maxplus2/synopsys/library/alt_syn/`<device family>`/lib};`
   `target_library = {`<technology library>`};`
   `symbol_library = {altera.sdb};`
   `link_library = {`<technology library>`};`
   `edifout_netlist_only = "true";`
   `edifout_power_and_ground_representation = "net";`
   `edifout_power_net_name = "VDD";`
   `edifout_ground_net_name = "GND";`
   `edifout_no_array = "false";`
   `edifin_power_net_name = "VDD";`
   `edifin_ground_net_name = "GND";`
   `compile_fix_multiple_port_nets = "true"`
   `bus_naming_style = "%s<%d>";`
   `bus_dimension_separator_style = "><";`
   `bus_inference_style = "%s<%d>";`

2. Specify one of the Design Compiler & FPGA Compiler Technology Libraries for the `target_library` and `link_library` parameters in the .synopsys_dc.setup file.

3. If you will instantiate architecture control logic functions from the alt_mf library, add the following line to your .synopsys_dc.setup file:

   `define_design_lib altera -path /usr/maxplus2/synopsys/library/alt_mf/lib`

   | If you wish to use the VHDL System Simulator (VSS) software to simulate a VHDL design containing alt_mf library functions, you must compile this library with the analyze_vss script. See Setting Up VSS Configuration Files for more information.

4. If you will use the DesignWare interface for FLEX® 6000, FLEX 8000, or FLEX 10K designs, enter additional lines in your .synopsys_dc.setup file, as described in Setting Up the DesignWare Interface.

5. Specify one of the following families for the <device family> variable in the `search_path` parameter: `max5000`, `max7000`, `max9000`, `flex6000`, `flex8000`, or `flex10k`.

6. If you wish to resynthesize a design for a different device family, modify the .synopsys_dc.setup file by following the steps described in Resynthesizing a Design Using the alt_vtl Library & a MAX+PLUS II SDF Output File.

| Go to MAX+PLUS® II/Synopsys Interface File Organization in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

## Setting Up the DesignWare Interface

The DesignWare interface synthesizes FLEX® 6000, FLEX 8000 and FLEX 10K designs by operator inference. It replaces the HDL operators +, -, >, <, >=, and <= with FLEX-optimized design implementations.

Altera provides DesignWare Synthetic Libraries that are pre-compiled for the current version of Synopsys tools. These library files are located in the /usr/maxplus2/synopsys/library/alt_syn/<device family>/lib directory.

To use the DesignWare interface with FLEX 6000, FLEX 8000 and FLEX 10K devices, follow these steps:

1. Add `synthetic_library` and `define_design_lib` parameters to your .synopsys_dc.setup configuration file and modify the `link_library` parameter as shown in Table 1 or Table 2.

   Table 1. DesignWare Parameters to Add to the .synopsys_dc.setup File for the Design Compiler Software
   Device Family | Parameters to Add to the .synopsys_dc.setup File
   FLEX 6000 | `synthetic_library = {flex6000`<speed grade>`.sldb};` `link_library = {flex6000`<speed grade>`.sldb flex6000`<speed grade>`.db};` `define_design_lib DW_FLEX6000`<speed grade>`-path /usr/maxplus2/synopsys/library/alt_syn/flex6000/lib/ dw_flex6000`<speed grade>``
   FLEX 8000 | `synthetic_library = {flex8000[`<speed grade>`].sldb};` `link_library = {flex8000[`<speed grade>`].sldb flex8000[`<speed grade>`].db};` `define_design_lib DW_FLEX8000[`<speed grade>`] -path /usr/maxplus2/synopsys/library/alt_syn/flex8000 /lib/dw_flex8000[`<speed grade>`]` `
   `
   FLEX 10K | `synthetic_library = {flex10k[`<speed grade >`].sldb};` `link_library = {flex10k[`<speed grade>`].sldb flex10k[`<speed grade>`].db};` `define_design_lib DW_FLEX10k[`<speed grade>`] -path /usr/maxplus2/synopsys/library/alt_syn/flex10k/lib /dw_flex10k[`<speed grade>`]`

   Table 2. DesignWare Parameters to Add to the .synopsys_dc.setup File for the FPGA Compiler Software
   Device Family | Parameters to Add to the .synopsys_dc.setup File
   FLEX 6000 | `synthetic_library = {flex6000` <speed grade>`_fpga.sldb};` `link_library = {flex6000`<speed grade>`_fpga.sldb flex6000`<speed grade>`_fpga.db};` `define_design_lib DW_FLEX6000`<speed grade>`_FPGA -path /usr/maxplus2/synopsys/library/alt_syn/flex6000
   /lib/dw_flex6000`<speed grade>`_fpga`
   FLEX 8000 | `synthetic_library = {flex8000[`<speed grade>`]_fpga.sldb};` `link_library = {flex8000[`<speed grade>`]_fpga.sldb flex8000[`<speed grade>`]_fpga.db};` `define_design_lib DW_FLEX8000[`<speed grade>`]_FPGA -path /usr/maxplus2/synopsys/library/alt_syn/flex8000/lib /dw_flex8000[`<speed grade>`]_fpga` `
   `
   FLEX 10K | `synthetic_library = {flex10k[`<speed grade>`]_fpga.sldb};` `link_library = {flex10k[`<speed grade>`]_fpga.sldb flex10k[`<speed grade>`]_fpga.db};` `define_design_lib DW_FLEX10k[`<speed grade>`]_FPGA -path /usr/maxplus2/synopsys/library/alt_syn/flex10k/lib /dw_flex10k[`<speed grade>`]_fpga` `
   `

2. Specify the libraries listed in Table 3 as your synthetic library and as the first of your link libraries.

   For FLEX 6000 devices, you must specify either `-2` or `-3` for the <speed grade> variable. For FLEX 8000 and FLEX 10K devices, you can specify `-2`, `-3`,`-4`, `-5`, or `-6`; or `-2`, `-3`, `-4`, or `-5`; respectively, for the <speed grade> variable. If you do not specify a speed grade for FLEX 8000 or FLEX 10K devices, the MAX+PLUS® II software selects the fastest device in the specified family as the target device.

   Table 3. FLEX 6000, FLEX 8000 & FLEX 10K DesignWare Synthetic Libraries
   Altera® Device Family | Synopsys Design Compiler | Synopsys FPGA Compiler
   --- | --- | ---
   FLEX 6000 Synthetic Library | flex6000-2.sldb flex6000-3.sldb | flex6000-2_fpga.sldb flex6000-3_fpga.sldb
   FLEX 8000 Synthetic Library | flex8000.sldb flex8000-2.sldb flex8000-3.sldb flex8000-4.sldb flex8000-5.sldb
   flex8000-6.sldb
   flex8000_fpga.sldb
   flex8000-2_fpga.sldb
   flex8000-3_fpga.sldb
   flex8000-4_fpga.sldb
   flex8000-5_fpga.sldb
   flex8000-6_fpga.sldb
   FLEX 10K Synthetic Library | flex10k.sldb flex10k-2.sldb flex10k-3.sldb flex10k-4.sldb flex10k-5.sldb | flex10k_fpga.sldb flex10k-2_fpga.sldb flex10k-3_fpga.sldb flex10k-4_fpga.sldb flex10k-5_fpga.sldb

3. If necessary, compile the DesignWare libraries, as described in Updating DesignWare Libraries. Altera provides pre-compiled DesignWare libraries, as described above. However, Altera also provides compatible source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare with any version of the Design Compiler. They also allow you to install components whose source is written in VHDL, even if you are licensed only for the HDL Compiler for Verilog.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Setting Up Design Compiler & FPGA Compiler Configuration Files
- DesignWare FLEX 8000 Synthesis Example
- Design Compiler & FPGA Compiler Technology Libraries

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

## Updating DesignWare Libraries

Although Altera provides DesignWare libraries that are pre-compiled for the current version of Synopsys tools, you may wish to recompile the libraries.

Altera provides compilable source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare software with any version of the Design Compiler or FPGA Compiler software.They also allow you to install components whose source is written in VHDL, even if you are licensed only for the Verilog HDL Compiler software.

Source files for the Design Compiler software are automatically installed in the following directories:

- /usr/maxplus2/synopsys/library/alt_syn/flex10k/src/dw_flex10k[<speed grade>]
- /usr/maxplus2/synopsys/library/alt_syn/flex8000/src/dw_flex8000[<speed grade>]
- /usr/maxplus2/synopsys/library/alt_syn/flex6000/src/dw_flex6000<speed grade>

Source files for the FPGA Compiler are automatically installed in the following directories:

- /usr/maxplus2/synopsys/library/alt_syn/flex10k/src/dw_flex10k[<speed grade>]_fpga
- /usr/maxplus2/synopsys/library/alt_syn/flex8000/src/dw_flex8000[<speed grade>]_fpga
- /usr/maxplus2/synopsys/library/alt_syn/flex6000/src/dw_flex6000<speed grade>_fpga

You can compile the VHDL source file for use with the appropriate library. Refer to Table 1 to determine which commands you should type at the UNIX prompt to compile the library.

Table 1. Commands for Compiling the Library
Device Family | Synopsys Compiler | Commands for Compiling the Library Note (1)
FLEX®6000 | Design Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex6000/ src/dw_flex6000`<speed grade>`dw_flex6000.script`
FPGA Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex6000/ src/dw_flex6000`<speed grade>`_fpga dw_flex6000.script`
FLEX 8000 | Design Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex8000/ src/dw_flex8000[`<speed grade>`] dw_flex8000.script`
FPGA Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex8000/ src/dw_flex8000[`<speed grade>`]_fpga dw_flex8000.script`
FLEX 10K | Design Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex10k/ src/dw_flex10k[`<speed grade>`] dw_flex10k.script`
FPGA Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex10k/ src/dw_flex10k[`<speed grade>`]_fpga dw_flex10k.script`

Notes:

1. For FLEX 6000 devices, you must specify either `-2` or `-3` for the <speed grade> variable. For FLEX 8000 and FLEX 10K devices, you must specify `-2`, `-3`,`-4`, `-5`, or `-6`; or `-1`, `-2`, `-3`, `-4`, or `-5`; respectively, for the <speed grade> variable.

| Go to the following topics for additional information:

- Setting Up the DesignWare Interface
- Setting Up the MAX+PLUS II/Synopsys Working Environment
- Setting Up Design Compiler & FPGA Compiler Configuration Files
- Setting Up VSS Configuration Files

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

## Design Compiler & FPGA Compiler Technology Libraries

The Altera®-provided Design Compiler and FPGA Compiler technology libraries contain primitives that the Synopsys compilers use to map your designs to the target device architecture. These primitives contain timing and area information that the Synopsys compilers use to meet area and performance requirements. Table 1 shows the functions provided in these libraries. Choose Primitives from the MAX+PLUS II Help menu for detailed information on these functions.

Altera recommends instantiating these functions directly in your designs only if the Synopsys compilers do not appear to recognize the functions when synthesizing your design, or if you prefer to hand-optimize certain portions of your design.

Table 1. Altera-Provided Primitives
Name Note (1), Note (2) | Description | Name | Description
--- | --- | --- | ---
`LCELL` | Logic cell buffer primitive | `EXP` | MAX® 5000, MAX 7000, and MAX 9000 Expander buffer primitive
`GLOBAL` | Global input buffer primitive | `SOFT` | Soft buffer primitive
`CASCADE` | FLEX® 6000, FLEX 8000, and FLEX 10K cascade buffer primitive | `OPNDRN` | FLEX 6000, FLEX 8000, and FLEX 10K Open-drain buffer primitive
`CARRY` | FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer primitive | `DFF` `DFFE` `DFFS` Note (2) | D-type flipflop with Clock Enable primitive
`LATCH` | Latch primitive | `TFF` `TFFE` `TFFS` Note (2) | T-type flipflop primitive
`TRIBUF` | Tri-state buffer primitive |  |

Notes:
(1) All buffer primitive names except `OPNDRN` must be prefixed with an "`A`" in FLEX 6000, FLEX 8000, and FLEX 10K designs. The `TRIBUF` primitive is equivalent to the `TRI` primitive in the MAX+PLUS II software.
(2) The `DFFE` and `TFFE` primitives include a Clock Enable input; the `DFFS` and `TFFS` primitives are equivalent to `DFF` and `TFF` primitives without Clear or Preset inputs. For designs that are targeted to FLEX 6000 devices, you should use the `DFFE` or `TFFE` primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the `DFFE6K` primitive.

| The VHDL simulation model /usr/maxplus2/synopsys/library/alt_pre/<device family>/src/<device family>_components.vhd file shows the exact cell and pin names for each device family. The Verilog HDL simulation file /usr/maxplus2/synopsys/library/alt_pre/verilog/src/altera.v shows the functionality of these cells.

Table 2 lists the technology library names.

Table 2. Altera Technology Libraries
Altera Device Family | Synopsys Design Compiler | Synopsys FPGA Compiler
--- | --- | ---
FLEX® 10K devices | flex10k.db flex10k-2.db flex10k-3.db flex10k-4.db flex10k-5.db | flex10k_fpga.db flex10k-2_fpga.db flex10k-3_fpga.db flex10k-4_fpga.db flex10k-5_fpga.db
FLEX 8000 devices | flex8000.db flex8000-2.db flex8000-3.db flex8000-4.db flex8000-5.db
flex8000-6.db
flex8000_fpga.db
flex8000-2_fpga.db
flex8000-3_fpga.db
flex8000-4_fpga.db
flex8000-5_fpga.db
flex8000-6_fpga.db
FLEX 6000 devices | flex6000-2.db flex6000-3.db | flex6000-2_fpga.db flex6000-3_fpga.db
MAX® 9000 devices | max9000.db | max9000_fpga.db
MAX 7000, MAX 7000E, MAX 7000S, & MAX 7000A devices | max7000.db | max7000_fpga.db
MAX 5000 & Classic® devices | max5000.db | max5000_fpga.db

| Go to MAX+PLUS® II/Synopsys Interface File Organization in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

## Altera VHDL & Verilog HDL alt_mf Logic Function Library

The alt_mf library contains behavioral VHDL and Verilog HDL models of the Altera® logic functions shown in Table 1. VHDL or Verilog HDL files that instantiate these functions can be simulated with the VHDL System Simulator (VSS) software or the Cadence Verilog-XL simulator, respectively, both before and after being compiled with the Synopsys Design Compiler or FPGA Compiler software.

Table 1. Altera-Provided Architecture Control Logic Functions
Name | Description
--- | ---
`a_8fadd` | 8-bit full adder
`a_8mcomp` | 8-bit magnitude comparator
`a_8count` | 8-bit up/down counter
`a_81mux` | 8-to-1 multiplexer

| For detailed information on these functions, choose Search for Help on from the MAX+PLUS® II Help menu and type the function name, without the "`a_`" prefix.

The behavioral descriptions of these four functions are contained in the /usr/maxplus2/synopsys/library/alt_mf/src directory, which contains the following files:

File: | Description:
mf.vhd | Contains behavioral VHDL descriptions of the logic functions.
mf_components.vhd | Contains VHDL Component Declarations for the logic functions.
mf.v | Contains behavioral Verilog HDL descriptions of the logic functions.

If you wish to simulate a VHDL design containing these logic functions, you can use the Altera-provided shell script analyze_vss to create a design library called altera. This library allows you to reference the functions through the VHDL Library and Use Clauses, which direct the Design Compiler or FPGA Compiler software to incorporate the library files when it compiles your top-level design file. The analyze_vss shell script creates the altera design library by analyzing the VHDL System Simulator (VSS) simulation models in the /usr/maxplus2/synopsys/library/alt_mf/lib directory. See Setting Up VSS Configuration Files for more information on using the analyze_vss shell script.

Complete VHDL and Verilog HDL behavioral descriptions of these logic functions are included in the mf.vhd and mf.v files so that you can optionally retarget your design to other technology libraries.

## Altera DesignWare FLEX 6000, FLEX 8000 & FLEX 10K Synthetic Libraries

The Altera® DesignWare interface for the FLEX® 6000, FLEX 8000, and FLEX 10K device families provides accurate area and timing prediction for designs that have been synthesized by the Synopsys design tools and targeted for FLEX devices. Altera's DesignWare interface also ensures that the area and timing information closely matches the final FLEX device implementation generated by the MAX+PLUS® II Compiler. The DesignWare interface synthesizes FLEX 6000, FLEX 8000 and FLEX 10K designs by operator inference. This interface supports bus widths of up to 32 bits, except adder functions, which support bus widths of up to 64 bits.

The Altera DesignWare interface for FLEX devices offers three major advantages to Synopsys designers:

- Automatic access to FLEX carry and cascade chain functions
- Optimal routing of FLEX designs
- Improved area and performance prediction capability in Synopsys tools

Table 1 lists the Altera DesignWare synthetic libraries for FLEX 6000, FLEX 8000, and FLEX 10K devices.

Table 1. FLEX 6000, FLEX 8000 & FLEX 10K DesignWare Synthetic Libraries
Altera Device Family | Synopsys Design Compiler | Synopsys FPGA Compiler
--- | --- | ---
FLEX 6000 Synthetic Library | flex6000-2.sldb flex6000-3.sldb | flex6000-2_fpga.sldb flex6000-3_fpga.sldb
FLEX 8000 Synthetic Library | flex8000.sldb flex8000-2.sldb flex8000-3.sldb flex8000-4.sldb flex8000-5.sldb
flex8000-6.sldb
flex8000_fpga.sldb
flex8000-2_fpga.sldb
flex8000-3_fpga.sldb
flex8000-4_fpga.sldb
flex8000-5_fpga.sldb
flex8000-6_fpga.sldb
FLEX 10K Synthetic Library | flex10k.sldb flex10k-2.sldb flex10k-3.sldb flex10k-4.sldb flex10k-5.sldb | flex10k_fpga.sldb flex10k-2_fpga.sldb flex10k-3_fpga.sldb flex10k-4_fpga.sldb flex10k-5_fpga.sldb

Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries. Refer to DesignWare FLEX 8000 Synthesis Example for an example showing how DesignWare synthesis affects design processing.

Table 2. FLEX 6000, FLEX 8000, and FLEX 10K Synthetic Library Functions
Name | Function
--- | ---
`flex_add` | Sum of A, B, and Carry-In
`flex_carry` | Carry of A, B, and Carry-In
`flex_sub` | Difference of A, B, and Borrow-In
`flex_borrow` | Borrow of A, B, and Borrow-In
`flex_gt,` `flex_sgt` | Greater than (`flex_gt` is unsigned; `flex_sgt` is signed)
`flex_carry_gt` | Greater than Carry
`flex_lt,` `flex_slt` | Less than (`flex_lt` is unsigned; `flex_slt` is signed)
`flex_carry_lt` | Less than Carry
`flex_gteq,``flex_sgteq` | Greater than or equal to (`flex_gteq` is unsigned; `flex_sgteq` is signed)
`flex_carry_gteq` | Greater than or equal to Carry
`flex_inc` | Incrementer (Count = Count + 1)
`flex_carry_inc` | Incrementer Carry (Count = Count + 1)
`flex_dec` | Decrementer (Count = Count - 1)
`flex_carry_dec` | Decrementer Carry (Count = Count - 1)
`flex_lteq, flex_slteq` | Less than or equal to (`flex_lteq` is unsigned; `flex_slteq` is signed)
`flex_carry_lteq` | Less than or equal to Carry
`flex_count` | Counter
`aflex_carry_count` | Counter Carry
`flex_add_sub` | Adder/Subtractor
`flex_inc_dec` | Incrementer/Decrementer
`flex_umult, flex_smult` | Multiplier (`flex_umult` is unsigned; `flex_smult` is signed)

| Go to the following sources for related information:

- Setting Up the DesignWare Interface in these MAX+PLUS II ACCESSSM Key topics
- Synopsys DesignWare Databook
- VHDL Compiler Reference Manual

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

## Altera Post-Synthesis Libraries

The /usr/maxplus2/synopsys/library/alt_post/syn/lib directory contains the post-synthesis library for technology mapping and timing back-annotation. The Altera®-provided alt_vtl.db file in this library contains over three dozen MAX+PLUS® II-generated logic functions.

## MAX+PLUS II/Synopsys Interface File Organization

Table 1 shows the MAX+PLUS® II/Synopsys interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during the MAX+PLUS II software installation. For information on the other directories that are created during the MAX+PLUS II software installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

| You must add the /usr/maxplus2/bin directory to the `PATH` environment variable in your .cshrc file in order to run the MAX+PLUS II software.

Table 1. MAX+PLUS II Directory Organization
Directory | Description
./synopsys/bin | Contains script programs to convert Synopsys timing constraints into MAX+PLUS II Assignment & Configuration File (.acf) format, and to analyze VHDL System Simulator simulation models.
./synopsys/config | Contains sample .synopsys_dc.setup and .synopsys_vss.setup files.
./synopsys/examples | Contains sample files, including those discussed in these ACCESS Key Guidelines.
./synopsys/library/alt_pre/<device family>/src | Contains VHDL simulation libraries for functional simulation of VHDL projects.
./synopsys/library/alt_pre/verilog/src | Contains the Verilog HDL functional simulation library for Verilog HDL projects.
./synopsys/library/alt_pre/vital/src | Contains the VITAL 95 simulation library. You use this library when you perform functional simulation of the design before compiling it with the MAX+PLUS II software.
./synopsys/library/alt_syn//<device family>/lib | Contains interface files for the MAX+PLUS II/Synopsys interface. Technology libraries in this directory allow the Design Compiler and FPGA Compiler to map designs to Altera® device architectures.
./synopsys/library/alt_mf/src | Contains behavioral VHDL models of some Altera macrofunctions, along with their component declarations. The `a_81mux`, `a_8count`, `a_8fadd`, and `a_8mcomp` macrofunctions are currently supported. Libraries in this directory allow you to instantiate, synthesize, and simulate these macrofunctions.
./synopsys/library/alt_post/syn/lib | Contains the post-synthesis library for technology mapping.
./synopsys/library/alt_post/sim/src | Contains the VHDL source files for the VITAL 95-compliant library. You use this library when you perform simulation of the design after compiling it with the MAX+PLUS II software.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II Project File Structure

In MAX+PLUS® II, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL™ TDF; or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by Synopsys and imported into MAX+PLUS II as an EDIF Input File.

MAX+PLUS II stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

## Synopsys Design Entry Flow

Figure 1 below shows the design entry flow for the MAX+PLUS® II/Synopsys interface.

Figure 1. MAX+PLUS II/Synopsys Design Entry Flow

| Altera-provided items are shown in blue.

## Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

Once you have created a VHDL design, you can use the Design Compiler or FPGA Compiler to synthesize and optimize it, and then generate an EDIF netlist file that can be processed with the MAX+PLUS II software.

To create a VHDL design that can be synthesized and optimized with the Design Compiler or FPGA Compiler, follow these steps:

1. Instantiate logic functions with a Component Instantiation, and include a Component Declaration for each function. Altera provides simulation models for the following types of logic functions:

   - Primitives in the Design Compiler & FPGA Compiler Technology Libraries. Go to Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.
   - Architecture Control Logic functions in the alt_mf library, which includes the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` functions. See MAX+PLUS II Architecture Control Logic Function Instantiation Example for VHDL for an example.
   - The DesignWare up/down counter function (`DW03_updn_ctr`). Go to DesignWare Up/Down Counter Function Instantiation Example for VHDL for an example.
   - RAM and ROM functions generated with the genmem utility. Go to Instantiating RAM & ROM Functions in VHDL for instructions.
   - The `clklock` megafunction, which is supported for selected FLEX 10K devices. This function is generated with the gencklk utility. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for instructions.
   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

   You can also instantiate any other Altera macrofunction or non-parameterized megafunction, i.e., functions not listed above, for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler or FPGA Compiler. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.

   | For information on MAX+PLUS II primitives, megafunctions, and macrofunctions, choose Primitives, Megafunctions/LPM, or Old-Style Macrofunctions from the MAX+PLUS II Help menu. When searching for information on the alt_mf library functions, drop the initial "`a_`" from the function name.

2. (Optional) If you instantiate a "black box" logic function for which no simulation/techology library support is available, create a hollow-body design description in order to prevent the Design Compiler or FPGA Compiler from issuing a warning message. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.

   | If you instantiate a "black box" logic function, you must create a Library Mapping File (.lmf) to map the function to an equivalent MAX+PLUS II function before you compile the project with the MAX+PLUS II software. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.

3. Once you have created a VHDL design, you can analyze it, synthesize it, (optional) perform a functional simulation, and generate an EDIF netlist file that can be imported into the MAX+PLUS II software. Go to the following topics for instructions:

   - Synthesizing & Optimizing VHDL & Verilog HDL Projects with Synopsys Software
   - Performing a Pre-Routing or Function Simulation with VSS Software

Installing the Altera-provided MAX+PLUS II/Synopsys Logic interface on your computer automatically creates the following VHDL sample files:

- /usr/maxplus2/examples/mentor/examples/ministate.vhd
- /usr/maxplus2/examples/mentor/examples/count8.vhd
- /usr/maxplus2/examples/mentor/examples/tstrom.vhd

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Primitive & Old-Style Macrofunction Instantiation Example for VHDL

You can instantiate the MAX+PLUS® II primitives listed in Design Compiler & FPGA Compiler Technology Libraries in VHDL designs. These primitives can be used to control synthesis in the MAX+PLUS II software. You can also instantiate MAX+PLUS II megafunctions and old-style macrofunctions.

| Go to the following topics for information and examples of how to instantiate functions that are not considered to be hollow bodies, including functions in the alt_mf library, RAM and ROM, and the `clklock` megafunction:

- Architecture Control Macrofunction Instantiation Example for VHDL
- Instantiating RAM & ROM Functions in VHDL
- Instantiating the clklock Megafunction in VHDL or Verilog HDL

Unlike other logic functions, MAX+PLUS II primitives do not need to be defined with Component Declarations unless you wish to simulate the design with the VHDL System Simulator (VSS) software. Any references to these primitives are resolved by the Synopsys compilers. All buffer primitives except the `ATRIBUF` and `TRIBUF` primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."

Figure 1 shows a 4-bit full adder with registered output that also instantiates an `AGLOBAL` or `GLOBAL` primitive. This figure also illustrates the use of global Clock and global Reset pins in the MAX 7000 architecture. The design uses an old-style `7483` macrofunction, which is represented as a hollow body named `fa4`.

Figure 1. 4-Bit Adder Design with Registered Output (adder.vhd)

    LIBRARY ieee;
       USE ieee.std_logic_1164.ALL;
       ENTITY adder IS
       PORT (a, b     : IN  STD_LOGIC_VECTOR(4 DOWNTO 1);
             clk, rst : IN  STD_LOGIC;
             cout     : OUT STD_LOGIC;
             regsum   : OUT STD_LOGIC_VECTOR(4 DOWNTO 1));
       END adder;
    ARCHITECTURE MAX7000 OF adder IS
    SIGNAL sum            : STD_LOGIC_VECTOR(4 DOWNTO 1);
    SIGNAL ci, gclk, grst : STD_LOGIC;
    -- Component Declaration for GLOBAL primitive
    -- For FLEX devices, global, a_in, and a_out should be replaced with
    -- aglobal, in1, and Y, respectively
    COMPONENT global
       PORT (a_in      : IN  STD_LOGIC;
             a_out     : OUT STD_LOGIC);
    END COMPONENT;
    -- Component Declaration for fa4 macrofunction
    COMPONENT fa4
       PORT (c0,a1,b1,a2,b2,a3,b3,a4,b4 : IN  STD_LOGIC;
             s1,s2,s3,s4,c4             : OUT STD_LOGIC);
    END COMPONENT;
    BEGIN
       ci <= '0';
    -- FA4 Component Instantiation
       u0: fa4
       PORT MAP (ci,a(1),b(1),a(2),b(2),a(3),b(3),a(4),b(4),
                 sum(1),sum(2),sum(3),sum(4),cout);
    -- GLOBAL Component Instantiation for Clock
    -- For FLEX devices, global should be replaced with aglobal
       u1: global
       PORT MAP (clk, gclk);
    -- GLOBAL Component Instantiation for Reset
    -- For FLEX devices, global should be replaced with aglobal
       u2: global
       PORT MAP (rst, grst);
    -- CLOCK process to create registered output
       clocked: PROCESS(gclk,grst)
       BEGIN
          IF grst = '0' THEN
          regsum <= "0000";
          ELSIF gclk'EVENT AND gclk = '1' THEN
                regsum <= sum;
          END IF;
       END PROCESS clocked;

    END MAX7000;

Before you can analyze the 4-bit adder design, you must first analyze the `fa4` description in Figure 1 with the Synopsys VHDL Compiler software. You can ignore the warning that is issued for any unknown function, including the `fa4` function in this example. If you wish, you can avoid receiving such warning messages by creating a hollow-body description of the function.

A hollow-body VHDL description combines an Entity Declaration with an empty or null Architecture Body. An empty Architecture Body contains the `ARCHITECTURE IS` clause, followed by the `BEGIN` and `END` keywords and a semicolon (;). It does not include any information about the design's function or operation. Figure 2 shows the hollow-body description for the `fa4` function.

Figure 2. Hollow-Body Description of a 4-Bit Full Adder (7483)
    LIBRARY ieee;
    USE     ieee.std_logic_1164.ALL;
    -- fa4 maps to 7483. The interface names do not have to match.

    ENTITY fa4 IS
    PORT (c0,a1,b1,a2,b2,a3,b3,a4,b4 : IN STD_LOGIC;
          s1,s2,s3,s4,c4             : OUT STD_LOGIC);
    END fa4;

    ARCHITECTURE map7483 OF fa4 IS
    BEGIN

    -- This architecture body is left blank, and will map to the
    -- 7483 macrofunction in MAX+PLUS II.

    END;

When you analyze the hollow-body design description with the Synopsys VHDL Compiler software, it produces a hollow-body component that contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.

You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the MAX+PLUS II software. After the VHDL Compiler software has successfully processed the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.

Figure 3. Synthesized Design Generated by the Design Compiler

However, before you compile the EDIF netlist file with the MAX+PLUS II software, you must create the adder.lmf file, shown in Figure 3, to map the `fa4` function to the equivalent MAX+PLUS II function (`7483`). You must then specify the LMF as LMF #2 in the expanded EDIF Netlist Reader Settings dialog box (Interfaces menu) (LMF #1 is altsyn.lmf). For more information about creating LMFs, refer to "Library Mapping Files (.lmf)" and "Library Mapping File Format" in MAX+PLUS II Help.

Figure 3. Library Mapping File Excerpt for fa4
    BEGIN
    FUNCTION 7483  (c0, a1, b1, a2, b2, a3, b3, a4, b4,)
    RETURNS        (s1, s2, s3, s4, c4)
    FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
                   "b3","a4", "b4")
    RETURNS        ("s1", "s2", "s3", "s4", "c4")
    END

When you compile the design with the MAX+PLUS II software, you can disregard the warning "`EDIF cell` <name>`already has LMF mapping so CONTENTS construct has been ignored`". To verify the global Clock and global Reset usage, as well as the number of logic cells used, see the adder.rpt Report File generated by the MAX+PLUS II Compiler.

## MAX+PLUS II Architecture Control Logic Function Instantiation Example for VHDL

You can instantiate Altera®-provided logic functions from the alt_mf library, which includes the `a_8fadd`, `a_8mcomp`, `a_8count`, and `a_81mux` functions, in VHDL designs. Altera provides behavioral descriptions of these functions that support pre-synthesis/pre-route simulation of your top-level design with the VHDL System Simulator (VSS).

When you instantiate one of these functions, you can either include a Component Declaration for the function, or use the Altera-provided shell script analyze_vss to create a design library called altera so that you can reference the functions through the VHDL Library and Use Clauses. The Library and Use Clauses direct the Design Compiler or FPGA Compiler to incorporate the library files when it compiles your top-level design file. The analyze_vss shell script creates the altera design library when it analyzes the VSS simulation models in the /usr/maxplus2/synopsys/library/alt_mf/lib directory. See Setting up VSS Configuration Files for more information on using the analyze_vss shell script.

Figure 1 shows an example of an 8-bit counter that is instantiated using the `a_8count` function.

Figure 1. Sample VHDL File with Logic Function Instantiation

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    LIBRARY altera;
    USE altera.maxplus2.ALL;
    ENTITY counter IS
    PORT (clock,ena,load,dnup,set,clear : IN STD_LOGIC;
       i    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
       q    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       cout : OUT STD_LOGIC);
    END counter;
    ARCHITECTURE structure OF counter IS
    BEGIN
       u1   : a_8count
       PORT MAP (a=>i(0), b=>i(1), c=>i(2), d=>i(3), e=>i(4),
                f=>i(5), g=>i(6), h=>i(7), ldn=>load, gn=>ena,
                dnup=>dnup, setn=>set, clrn=>clear, clk=>clock,
                qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3), qe=>q(4),
                qf=>q(5), qg=>q(6), qh=>q(7), cout=>cout);
    END structure;
    CONFIGURATION conf OF counter IS
       FOR structure
       END FOR;
    END conf;

## DesignWare Up/Down Counter Function Instantiation Example for VHDL

The Altera DesignWare Libraries for FLEX devices allow you to instantiate the `DW03_updn_ctr` function, which is the same as the Synopsys `DW03` up/down counter. This function allows you to use the same VHDL code regardless of which FLEX® device is targeted.

Figure 1 shows a VHDL file excerpt with `DW03_updn_ctr` instantiation.

Figure 1. VHDL File Excerpt with Up/Down Counter Instantiation
    LIBRARY ieee,DW03;
    USE ieee.std_logic_1164.all;
    USE DW03.DW03_components.all;
    ENTITY updn_4 IS
       PORT (D : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
          UP_DN, LD, CE, CLK, RST: IN STD_LOGIC;
          TERCNT : OUT STD_LOGIC;
          Q      : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0));
    END updn_4;
    ARCHITECTURE structure OF updn_4 IS
    BEGIN
       u0: DW03_updn_ctr
       GENERIC MAP(width => 4)
       PORT MAP (data => d, clk => clk, reset => rst, up_dn => up_dn,
                 load => ld, tercnt => tercnt, cen => ce, count => q);
    END structure;

| Go to Setting Up the DesignWare Interface in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

## Instantiating RAM & ROM Functions in VHDL

The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. You can use the Altera®-provided genmem utility to generate functional simulation models and timing models for these functions. Type `genmem` at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.

To instantiate a RAM or ROM function in VHDL, follow these steps:

1. Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:

   `genmem` <memory type>`` <memory size>`-vhdl`

   For example: `genmem asynrom 256x15 -vhdl`

2. Create a VHDL design that incorporates the text from the genmem-generated Component Declaration, <memory name>.cmp, and instantiate the <memory name> function.

   Figure 1 shows a VHDL design that instantiates asyn_rom_256x15.vhd, a 256 x 15 ROM function.

   Figure 1. VHDL Design File with ROM Instantiation (tstrom.vhd)
       LIBRARY ieee;
       USE ieee.std_logic_1164.all;
       ENTITY tstrom IS
               PORT (
                 addr    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 memenab : IN STD_LOGIC;
                 q       : OUT STD_LOGIC_VECTOR (14 DOWNTO 0));
       END tstrom;
       ARCHITECTURE behavior OF tstrom IS

       COMPONENT asyn_rom_256x15
       -- pragma translate_off
            GENERIC (LPM_FILE : string);
       -- pragma translate_on
            PORT (Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                  MemEnab : IN STD_LOGIC;
                  Q       : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
            );
       END COMPONENT;
       BEGIN

          u1: asyn_rom_256x15
       -- pragma translate_off
               GENERIC MAP (LPM_FILE => "u1.hex")
       -- pragma translate_on
          PORT MAP (Address => addr, MemEnab => memenab, Q =>q);
       END behavior;

3. (Optional for RAM functions) Specify an initial memory content file:

   - For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Generic Map Clause, with the `LPM_FILE` parameter. See Figure 1. The filename must be the same as the instance name; e.g., the `u1` instance name must be unique throughout the whole project, and must contain only valid VHDL name characters. The initialization file must reside in the directory containing the project's design files.

   - For RAM functions, specifying a memory initialization file is optional. If you want to use it, you must specify it in the Generic Map Clause as described above. If you do not use an initialization file, you should not declare or use the Generic Clause.

   1. The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use a MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.
   2. If you use an Intel hexadecimal format file and wish to simulate the design with the VHDL System Simulator (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.

4. In the VHDL design file, add the compiler directive `-- pragma translate_off` before the Generic Clause and Generic Map Clause, and add `-- pragma translate_on` after the Generic Clause and Generic Map Clause. These directives tell the VHDL Compiler software when to stop and start synthesizing. For example, in Figure 1, the `--pragma translate_off` directive instructs the VHDL Compiler software to skip syntax checking until the `--pragma translate_on` directive is read.

5. Because the VHDL Compiler software does not support the data type `string` for the Generic Clause, you must also enter the following command before you read the design:

   `hdlin_translate_off_skip_text=true`

6. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that can be used by the Synopsys Design Compiler and FPGA Compiler software. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:

   `read -f db flex10k`[<speed grade>]`.db` `update_lib flex10k`[<speed grade>] <RAM/ROM function name>`.lib`

7. (Optional) Enter the following command to update your flex10k[<speed grade>].db file with the RAM/ROM timing information:

   `write_lib flex10k`[<speed grade>]`-o flex10k.db`

8. When you generate the EDIF netlist file from the design, include the bus structure from the RAM or ROM function(s). Go to Setting Up Synopsys Configuration Files for more information.

9. Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating the clklock Megafunction in VHDL or Verilog HDL

MAX+PLUS® II interfaces with other EDA tools support the `clklock` phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility. Type `gencklk -h` at the UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).

The gencklk utility allows parameters for the `clklock` function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the `clklock` function name; therefore, the values do not need to be declared explicitly.

To instantiate the `clklock` megafunction in VHDL or Verilog HDL, go through the following steps:

1. Type the following command at the UNIX prompt to generate the `clklock_`x`_`y file, where x is the ClockBoost™ value and y is the input frequency in MHz:

   | Type `gencklk` <ClockBoost> <input frequency>`-vhdl` for VHDL designs.

   or:

   | Type `gencklk` <ClockBoost> <input frequency> `-verilog` for Verilog HDL designs.

   Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the `clklock` megafunction.

2. Create a design file that instantiates the `clklock``_`x`_`y function. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.

Figures 1 and 2 show a `clklock` function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.

Figure 1. VHDL Design File with clklock Instantiation (count8.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY altera;
    USE altera.maxplus2.all;     --  Include Altera Component Declarations
    ENTITY count8 IS
       PORT (a    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             ldn  : IN STD_LOGIC;
             gn   : IN STD_LOGIC;
             dnup : IN STD_LOGIC;
             setn : IN STD_LOGIC;
             clrn : IN STD_LOGIC;
             clk  : IN STD_LOGIC;
             co   : OUT STD_LOGIC;
             q    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END count8;
    ARCHITECTURE structure OF count8 IS
       signal clk2x : STD_LOGIC;
    COMPONENT clklock_2_40
       PORT (
          INCLK : IN STD_LOGIC;
          OUTCLK : OUT STD_LOGIC
       );
    END COMPONENT;
    BEGIN
       u1: clklock_2_40
       PORT MAP (inclk=>clk, outclk=>clk2x);
       u2: a_8count
       PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
                 e=>a(4), f=>a(5), g=>a(6), h=>a(7),
                 clk=>clk2x,
                 ldn=>ldn,
                 gn=>gn,
                 dnup=>dnup,
                 setn=>setn,
                 clrn=>clrn,
                 qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
                 qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
                 cout=>co);
     END structure;

Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v)
    `timescale 1ns / 10ps
    module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q);
    output          co;
    output[7:0]     q;
    input[7:0]      a;
    input           ldn, gn,dnup, setn, clrn, clk;
    wire            clk2x;
    clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) );
    A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]),
                 .G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
                 .SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
                 .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
                 .QH(q[7]), .COUT(co) );
    endmodule

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- Verilog HDL templates are available with the Verilog HDL Templates command (Templates menu). These templates are also available in the ASCII verilog.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your Verilog HDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

Once you have created a Verilog HDL design, you can use the Design Compiler or FPGA Compiler to synthesize and optimize it, and then generate an EDIF netlist file that can be processed with the MAX+PLUS II software.

To create a Verilog HDL design that can be synthesized and optimized with the Design Compiler or FPGA Compiler, follow these steps:

1. Instantiate logic functions with a Module Instantiation, and include a Module Declaration for each function. Altera provides simulation models for the following types of logic functions:

   - Primitives in the Design Compiler & FPGA Compiler Technology Libraries. Go to Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL for an example.
   - Architecture Control Logic functions in the alt_mf library, which includes the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` functions. See MAX+PLUS II Architecture Control Logic Function Instantiation Example for Verilog HDL for an example.
   - RAM and ROM functions generated with the genmem utility. Go to Instantiating RAM & ROM Functions in VHDL for instructions.
   - The `clklock` megafunction, which is supported for selected FLEX 10K devices. This function is generated with the gencklk utility. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for instructions.
   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

   You can also instantiate any other Altera macrofunction or non-parameterized megafunction, i.e., functions not listed above, for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler or FPGA Compiler. See Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL for an example.

   | For information on MAX+PLUS II primitives, megafunctions, and macrofunctions, choose Primitives, Megafunctions/LPM, or Old-Style Macrofunctions from the MAX+PLUS II Help menu. When searching for information on the alt_mf library functions, drop the initial "`a_`" from the function name.

2. (Optional) If you instantiate a "black box" logic function for which no simulation/techology library support is available, create a hollow-body design description in order to prevent the Design Compiler or FPGA Compiler from issuing a warning message. See Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL for an example.

   | If you instantiate a "black box" logic function, you must create a Library Mapping File (.lmf) to map the function to an equivalent MAX+PLUS II function before you compile the project with the MAX+PLUS II software. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.

3. Once you have created a VHDL design, you can analyze it, synthesize it, (optional) perform a functional simulation, and generate an EDIF netlist file that can be imported into the MAX+PLUS II software. Go to the following topics for instructions:

   - Synthesizing & Optimizing VHDL & Verilog HDL Projects with Synopsys Software
   - Performing a Pre-Routing or Function Simulation with VSS Software

Installing the Altera-provided MAX+PLUS II/Synopsys Logic interface on your computer automatically creates the following VHDL sample files:

- /usr/maxplus2/examples/mentor/examples/ministate.v
- /usr/maxplus2/examples/mentor/examples/count8.v
- /usr/maxplus2/examples/mentor/examples/tstrom.v

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL

You can instantiate the MAX+PLUS® II primitives listed in Design Compiler & FPGA Compiler Technology Libraries in Verilog HDL designs. These primitives can be used to control synthesis in the MAX+PLUS II software. You can also instantiate MAX+PLUS II megafunctions and old-style macrofunctions.

| Go to the following topics for information and examples of how to instantiate functions that are not considered to be hollow bodies, including functions in the alt_mf library, RAM and ROM, and the `clklock` megafunction:

- Architecture Control Macrofunction Instantiation Example for Verilog HDL
- Instantiating RAM & ROM Functions in Verilog HDL
- Instantiating the clklock Megafunction in VHDL or Verilog HDL

Unlike other logic functions, MAX+PLUS II primitives do not need to be defined with hollow-body functions unless you wish to simulate the design with the VHDL System Simulator (VSS) software. Any references to these primitives are resolved by the Synopsys compilers. All buffer primitives except the `ATRIBUF` and `TRIBUF` primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."

Figure 1 shows a 4-bit full adder with registered output that also instantiates an `AGLOBAL` or `GLOBAL` primitive. This figure also illustrates the use of global Clock and global Reset pins in the MAX 7000 architecture. The design uses an old-style `7483` macrofunction, which is represented as a hollow body named `fa4`.

Figure 1. 4-Bit Adder Design with Registered Output (adder.v)
    module adder (a, b, clk, rst, cout, regsum);

    output       cout;
    output[4:1]  regsum;
    input[4:1]   a, b;
    input        clk, rst;
    wire[4:1]    sum;
    reg[4:1]     regsum_int;
    wire         grst, gclk;
    wire         ci;
    assign       ci = 0;
    // module instantiation
    fa4    u0  ( .c0(ci), .a1(a[1]), .b1(b[1]), .a2(a[2]),
                 .b2(b[2]), .a3(a[3]), .b3(b[3]), .a4(a[4]),
                 .b4(b[4]), .s1(sum[1]), .s2(sum[2]),
                 .s3(sum[3]), .s4(sum[4]), .c4(cout));
    // For FLEX devices, GLOBAL, A_IN, and A_OUT should be replaced
    // with AGLOBAL, IN1, and Y, respectively
    GLOBAL  u1 ( .A_IN(clk), .A_OUT(gclk));
    GLOBAL  u2 ( .A_IN(rst), .A_OUT(grst));
    always @(posedge gclk or negedge grst)
            if ( !grst )
                    regsum_int = 4'b0;
            else regsum_int = sum;
    assign regsum = regsum_int;
    endmodule
    // module declaration for fa4 module
    module fa4 ( c0, a1, b1, a2, b2, a3, b3, a4, b4, s1, s2, s3, s4, c4);
       output    s1, s2, s3, s4, c4;
       input     c0, a1, b1, a2, b2, a3, b3, a4, b4;
       endmodule
    // module declaration for GLOBAL primitive
    // For FLEX devices, GLOBAL, A_IN, and A_OUT should be replaced
    // with AGLOBAL, IN1, and Y, respectively
    module GLOBAL (A_OUT, A_IN);
       input       A_IN;
       output      A_OUT;
       endmodule

You can analyze the 4-bit adder design with the Synopsys HDL Compiler for Verilog software. The hollow-body description of the `fa4` function is required. It contains port declarations and does not include any information about the design's function or operation. However, the hollow-body description can be in the design file, as shown in Figure 1, or in a separate file, as shown in Figure 2.

Figure 2. Hollow-Body Description of a 4-Bit Full Adder (7483)
    module fa4 ( c0, a1, b1, a2, b2, a3, b3, a4, b4, s1, s2, s3, s4, c4);
       output    s1, s2, s3, s4, c4;
       input     c0, a1, b1, a2, b2, a3, b3, a4, b4;
       endmodule

If the hollow-body description is in a separate file, you must analyze it before analyzing the higher-level function with the HDL Compiler for Verilog to produce a hollow-body component. This component contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.

You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the MAX+PLUS II software. After the HDL Compiler for Verilog software has successfully processed the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.

Figure 3. Synthesized Design Generated by the Design Compiler

However, before you compile the EDIF netlist file with the MAX+PLUS II software, you must create the adder.lmf file, shown in Figure 3, to map the `fa4` function to the equivalent MAX+PLUS II function (`7483`). You must then specify the LMF as LMF #2 in the expanded EDIF Netlist Reader Settings dialog box (Interfaces menu) (LMF #1 is altsyn.lmf). For more information about creating LMFs, refer to "Library Mapping Files (.lmf)" and "Library Mapping File Format" in MAX+PLUS II Help.

Figure 3. Library Mapping File Excerpt for fa4
    BEGIN
    FUNCTION 7483  (c0, a1, b1, a2, b2, a3, b3, a4, b4,)
    RETURNS        (s1, s2, s3, s4, c4)
    FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
                   "b3","a4", "b4")
    RETURNS        ("s1", "s2", "s3", "s4", "c4")
    END

When you compile the design with the MAX+PLUS II software, you can disregard the warning "`EDIF cell` <name>`already has LMF mapping so CONTENTS construct has been ignored`". To verify the global Clock and global Reset usage, as well as the number of logic cells used, see the adder.rpt Report File generated by the MAX+PLUS II Compiler.

## MAX+PLUS II Architecture Control Logic Function Instantiation Example for Verilog HDL

You can instantiate Altera®-provided logic functions from the alt_mf library, which includes the `a_8fadd`, `a_8mcomp`, `a_8count`, and `a_81mux` functions, in Verilog HDL designs. Altera provides behavioral Verilog HDL descriptions of these functions.

Figure 1 shows an example of an 8-bit counter that is instantiated using the `a_8count` function. Because Verilog HDL is case-sensitive, be sure to use uppercase letters for all of the macrofunction's module names and port names.

Figure 1. Sample Verilog HDL File with Logic Function Instantiation (counter.v)

    module counter (clock, ena, load, dnup, set, clear, i, q, cout);
    output          cout;
    output[7:0]     q;
    input[7:0]      i;
    input           clock, ena, load, dnup, set, clear;
    A_8COUNT u1    (.A(i[0]), .B(i[1]), .C(i[2]), .D(i[3]),
                    .E(i[4]), .F(i[5]), .G(i[6]), .H(i[7]),
                    .LDN(load), .GN(ena), .DNUP(dnup), .SETN(set),
                    .CLRN(clear), .CLK(clock), .QA(q[0]), .QB(q[1]),
                    .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]),
                    .QG(q[6]), .QH(q[7]), .COUT(cout) );
    endmodule

The sample file shown in Figure 1 can be synthesized with the Design Compiler or FPGA Compiler. You can also simulate it with the Cadence Verilog-XL Simulator by typing the following command at the dc_shell prompt:

`verilog counter.v /usr/maxplus2/synopsys/library/alt_mf/src/mf.v`

## Instantiating RAM & ROM Functions in Verilog HDL

The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. You can use the Altera®-provided genmem utility to generate functional simulation models and timing models for these functions. Type `genmem` at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.

To instantiate a RAM or ROM function in Verilog HDL, follow these steps:

1. Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:

   `genmem` <memory type>`` <memory size>`-verilog`

   For example: `genmem asynrom 256x15 -verilog`

2. Create a Verilog HDL design that instantiates the <memory name> function.

   Figure 1 shows a Verilog HDL design that instantiates asyn_rom_256x15.v, a 256 x 15 ROM function.

   Figure 1. Verilog HDL File with ROM Instantiation (tstrom.v)
       module tstrom (addr, enab, q);
       parameter LPM_FILE = "u1.hex";
       input [7:0] addr;
       input enab;
       output [14:0] q;
       asyn_rom_256x15
       // synopsys translate_off
                  #(LPM_FILE)
       // synopsys translate_on
             u1  (.Address(addr), .Q(q), .MemEnab(enab));

       endmodule

3. (Optional for RAM functions) Specify an initial memory content file:

   - For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Parameter Statement, with the `LPM_FILE` parameter. See Figure 1. The filename must be the same as the instance name; e.g., the `u1` instance name must be unique throughout the whole project. The initialization file must reside in the directory containing the project's design files.

   - For RAM functions, specifying a memory initialization file is optional. If you want to use it, you must specify it in a Parameter Statement, as described above.

   1. The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use a MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.
   2. If you use an Intel hexadecimal format file and wish to simulate the design with the VHDL System Simulator (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.

4. In the Verilog HDL design, add `// synopsys translate_off` before the Parameter Statement, and add `// synopsys translate_on` after the Parameter Statement. These directives tell the HDL Compiler for Verilog when to stop and start synthesizing. See Figure 1.

5. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that can be used by the Synopsys Design Compiler and FPGA Compiler software. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:

   `read -f db flex10k`[<speed grade>]`.db` `update_lib flex10k`[<speed grade>] <RAM/ROM function name>`.lib`

6. (Optional) Include the following command to update your flex10k[<speed grade>].db file with the RAM/ROM timing information:

   `write_lib flex10k[`<speed grade>`] -o flex10k.db`

7. When you generate the EDIF netlist file from the design, include the bus structure from the RAM or ROM function(s). Go to Setting Up Synopsys Configuration Files for more information.

8. Continue with the steps necessary to complete your Verilog HDL design, as described in Creating Verilog HDL Designs for Use with MAX+PLUS II Software.

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Synopsys Software

The MAX+PLUS® II Compiler can process a VHDL or Verilog HDL file that has been synthesized by the Synopsys Design Compiler or FPGA Compiler software, saved as an EDIF 2 0 0 or 3 0 0 netlist file, and imported into the MAX+PLUS II software. The procedure below explains how to run Synopsys tools separately from MAX+PLUS II Software.

| You can also run Synopsys tools from within the MAX+PLUS II software to automatically generate and import an EDIF file. Refer to Running Synopsys Compilers from MAX+PLUS II Software for more information. In addition, if your MAX+PLUS II development system includes VHDL or Verilog HDL synthesis support, the MAX+PLUS II Compiler can directly synthesize VHDL or Verilog HDL logic. For more information, go to MAX+PLUS II VHDL or Verilog HDL Help.

The following steps explain how to synthesize and optimize a VHDL or Verilog HDL design for use with MAX+PLUS II software:

1. Be sure to set up your design environment correctly. This step includes specifying the target device family for the design. See the following topics:
   - Setting Up the Synopsys/MAX+PLUS II Working Environment
   - Setting Up the Design Compiler and FPGA Compiler Configuration Files
   - Setting Up the DesignWare Interface
   - Setting Up the VSS Configuration Files

2. Create a VHDL file, <design name>.vhd, or a Verilog HDL design, <design name>.v, using the MAX+PLUS II Text Editor or another standard text editor and save it in a project directory under your login directory. See the following topics for instructions:
   - Creating VHDL Designs for Use with MAX+PLUS II Software.
   - Creating Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Start the Design Compiler or FPGA Compiler software by typing either `dc_shell` or `fpga_shell` at the command line, respectively. To work within the graphical user interface, type `design_analyzer` for either tool.

4. Analyze and then compile the design with the Design Compiler, FPGA Compiler, or Design Analyzer software. The VHDL Compiler or HDL Compiler for Verilog software automatically translates the design into Synopsys database (.db) format. Specific steps are necessary for some types of projects before you process the design:

   1. If your FLEX 10K design includes RAM or ROM functions, follow these steps:

      1. (VHDL designs only) Because the VHDL Compiler software does not support the data type `string` for the Generic Clause, you must also enter the following command at the `dc_shell` prompt before you read the design:

         `hdlin_translate_off_skip_text=true`

      2. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that can be used by the Synopsys Design Compiler and FPGA Compiler software. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:

         `read -f db flex10k`[<speed grade>]`.db` `update_lib flex10k`[<speed grade>] <RAM/ROM function name>`.lib`

      3. (Optional) Enter the following command to update your flex10k[<speed grade>].db file with the RAM/ROM timing information:

         `write_lib flex10k`[<speed grade>]`-o flex10k.db`

      See Instantiating RAM & ROM Functions in VHDL or Instantiating RAM & ROM functions in Verilog HDL for additional information.

   2. If you wish to allow the FPGA Compiler to perform N-input look-up table (LUT) optimization for a FLEX 6000, FLEX 8000, or FLEX 10K design, enter the following command at the `dc_shell` prompt before compiling the design:

      `edifout_write_properties_list = "lut function"`

      Go to Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000, or FLEX 10K Devices for more information.

   3. If you wish to enter resource assignments, go to Entering Resource Assignments.

   4. If you wish to direct the Design Compiler or FPGA Compiler to use sum-of-products logic in processing a MAX 7000 or MAX 9000 design, type the following commands at the `dc_shell` prompt before compiling the design:

      `set_structure false`
      `set_flatten -effort low`

      See MAX 7000 & MAX 9000 Synthesis Example for more information.

      For additional information on how the Design Compiler and FPGA Compiler synthesize and optimize a design, see the following topics:

      - Synopsys Design Compiler Reference Manual or Design Analyzer Reference Manual
      - DesignWare FLEX 8000 Synthesis Example

5. (Optional) View the optimized project with the Design Analyzer. The Design Analyzer uses the altera.sdb library to display optimized projects generated by the Design Compiler or FPGA Compiler.

6. (Optional) To view Synopsys-generated timing information and generate a file detailing primitive usage, type the following commands:

   `report_timing`
   `report_reference > <filename>```

7. (Optional) To functionally verify the project prior to processing with the MAX+PLUS II software, save the design as a VHDL netlist file, and simulate it as described in Performing a Pre-Routing or Functional Simulation with VSS Software.

8. Save the optimized project as an EDIF netlist file with the extension .edf.

9. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with the MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Synopsys interface on your computer automatically creates the following sample VHDL and Verilog HDL files:

- /usr/maxplus2/synopsys/examples/ministate.vhd
- /usr/maxplus2/synopsys/examples/ministate.v

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Resynthesizing a Design Using the alt_vtl Library and a MAX+PLUS II SDF Output File
- Programming Altera Devices

## MAX 7000 & MAX 9000 Synthesis Example

The MAX® 7000 (including MAX 7000E, MAX 7000S, and MAX 7000A) and MAX 9000 device families have a sum-of-products architecture. To obtain optimum timing and area results, you can direct the Synopsys Design Compiler or FPGA Compiler software to synthesize your logic into a sum-of-products form. To assist the Synopsys compilers in meeting the timing and area constraints of your designs, the Altera® technology libraries provide models that approximate the timing of the MAX 7000 and MAX 9000 logic cells.

Figure 1 shows two timing models: the standard Altera MAX 7000 timing model and a Synopsys timing model that approximates the MAX 7000 model. The Synopsys model is built on the following three conditions and assumptions:

1. The combinatorial delay in logic cells has been equally divided between product terms and `OR` gates. Because the product-term delay equals the OR-gate delay, the Synopsys compilers treat them equally, producing a sum-of-products structure. On top of this structure, inverters are used where necessary.

2. A shared expander product term is always used to create combinatorial logic.

3. The Synopsys Design Compiler and FPGA Compiler software do not distinguish between array and global Clocks. Therefore, to estimate setup and hold timing most accurately, you must instantiate GLOBAL buffers to indicate a global clock in either your VHDL or Verilog HDL design.

Figure 1. Standard MAX 7000 Timing Model vs. Synopsys Approximation of Timing Model

If you wish to direct the Synopsys Design Compiler or FPGA Compiler software to produce sum-of-products logic that approximates the MAX 7000 or MAX 9000 timing model, you can type the following dc_shell prompt commands at the command line before compiling the design:

`set_structure false`

`set_flatten -effort low`

When `set_structure` is set to `false`, structuring is turned off, and the Synopsys Design Compiler and FPGA Compiler software cannot factor and share logic between functions. If you do not enter these commands, the Synopsys compilers may add logic, which can create additional area and timing delays.

Figure 2 shows a combinatorial design that is predictable when structuring is turned off, but is unpredictable when structuring is turned on.

Figure 2. Nonstructured vs. Structured Combinatorial Design

When you use `low` as the argument to the `set_flatten -effort` command, the Synopsys compilers use the shortest compilation time to create the sum-of-products implementation of your design. If you use the `medium` or `high` argument, the Synopsys compilers create optimally flattened designs, but usually require greater compilation time and offer little improvement in timing and area results.

You can type `report_timing` after compilation to view Synopsys-generated timing information.

If you wish to calculate the area of your design, you can obtain an approximate logic cell count in several ways. Altera recommends that you add the number of registers and combinatorial outputs in a design. Depending on your design, this number may be slightly lower than the final number reported by the MAX+PLUS II software.

To create a file detailing primitive usage in the design, type `report_reference>` <filename> after Synopsys compilation.

| To obtain accurate timing information about your design, you must use the MAX+PLUS II Timing Analyzer to analyze your design. For accurate area information, consult the Report File (.rpt) generated by the MAX+PLUS II software.

| Refer to the following sources for related information:

- Synopsys Design Compiler Reference Manual or Synopsys Command Reference Manual
- FPGA Compiler User Guide
- Synthesizing & Optimizing VHDL & Verilog HDL Pojects with Synopsys Software

  | Go to MAX Devices, which is available on the web, for additional information:

## DesignWare FLEX 8000 Synthesis Example

Figure 1 shows a sample VHDL design, design_one.vhd, which illustrates component inference with the DesignWare interface for FLEX® 8000 devices.

Figure 1. VHDL Design File (design_one.vhd)
This design illustrates the sum of A + B.
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.ALL;
    ENTITY design_one IS
       PORT (a,b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
             f   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END design_one;
    ARCHITECTURE add_design OF design_one IS
    BEGIN
     f <= a + b;
    END add_design;

When the VHDL Compiler or the HDL Compiler for Verilog software analyzes and elaborates the design, it replaces the "+" operator with its synthetic operator equivalent.

Figure 2 shows the design as it appears in the Design Analyzer software after it has been analyzed and elaborated by the VHDL Compiler software.

Figure 2. design_one.vhd after Analysis & Elaboration

When you synthesize a design, the Design Compiler or FPGA Compiler software uses the synthetic library to match the synthetic operator to the FLEX-optimized logical implementation in the technology library. The Synopsys Design Compiler or FPGA Compiler software then instantiates and interconnects the correct number of `flex_add` and `flex_carry` functions to produce the 8-bit adder shown in Figure 1. When you save a compiled design as a VHDL, Verilog HDL or EDIF file, the file preserves the number of `flex_add` and `flex_carry` functions, as well as their interconnections. Consequently, area and performance predictions that you make in the Synopsys design environment closely match the final MAX+PLUS® II result.

Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries.

Table 2. FLEX 6000, FLEX 8000, and FLEX 10K Synthetic Library Functions
Name | Function
--- | ---
`flex_add` | Sum of A, B, and Carry-In
`flex_carry` | Carry of A, B, and Carry-In
`flex_sub` | Difference of A, B, and Borrow-In
`flex_borrow` | Borrow of A, B, and Borrow-In
`flex_gt,` `flex_sgt` | Greater than (`flex_gt` is unsigned; `flex_sgt` is signed)
`flex_carry_gt` | Greater than Carry
`flex_lt,` `flex_slt` | Less than (`flex_lt` is unsigned; `flex_slt` is signed)
`flex_carry_lt` | Less than Carry
`flex_gteq,``flex_sgteq` | Greater than or equal to (`flex_gteq` is unsigned; `flex_sgteq` is signed)
`flex_carry_gteq` | Greater than or equal to Carry
`flex_inc` | Incrementer (Count = Count + 1)
`flex_carry_inc` | Incrementer Carry (Count = Count + 1)
`flex_dec` | Decrementer (Count = Count - 1)
`flex_carry_dec` | Decrementer Carry (Count = Count - 1)
`flex_lteq, flex_slteq` | Less than or equal to (`flex_lteq` is unsigned; `flex_slteq` is signed)
`flex_carry_lteq` | Less than or equal to Carry
`flex_count` | Counter
`aflex_carry_count` | Counter Carry
`flex_add_sub` | Adder/Subtractor
`flex_inc_dec` | Incrementer/Decrementer
`flex_umult, flex_smult` | Multiplier (`flex_umult` is unsigned; `flex_smult` is signed)

Figure 3 shows design_one.vhd after it has been synthesized with the Design Compiler.

Figure 3. design_one.vhd Synthesized & Resolved for FLEX 6000, FLEX 8000 & FLEX 10K Architecture

After you save the design as an EDIF Input File (.edf) and process it with the MAX+PLUS II Compiler, the Compiler replaces instances of `flex_add` and `flex_carry` with FLEX-optimized versions, as shown in Figure 4. The MAX+PLUS II Compiler maps these functions into a single logic element (LE). The result is a high-speed 8-bit adder that fits into 8 LEs.

Figure 4. One Slice of the design_one 8-bit Adder Design with Optimized FLEX 8000 Functions

| Refer to the following sources for related information on DesignWare and the Synopsys VHDL Compiler:

- Synopsys DesignWare Databook
- VHDL Compiler Reference Manual

| Go to FLEX Devices, which is available on the web, for additional information:

## Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000 & FLEX 10K Devices

The Synopsys FPGA Compiler software supports an N-input look-up table (LUT) function that improves the quality of the results and the predictability of delay and resource estimates. All Altera® FPGA Compiler libraries for FLEX® 6000, FLEX 8000, and FLEX 10K devices support the N-input LUT function.

Figure 1 shows a sample command sequence that FPGA Compiler might require for N-input LUT optimization. To use N-input LUT optimization, include the `edifout_write_properties_list = "lut_function"` command.

Figure 1. Sample Command Sequence for N-Input LUT Optimization
`read -f vhdl` <design name>`.vhd` `current_design =` <design name>`` `set_max_area 0` `uniquify` `ungroup -all -flatten`
`compile -ungroup_all`
`report_area >` <design name>`.rpa`
`report_fpga >` <design name>`.rpf`
`report_cell >` <design name>`.rpc`
`edifout_write_properties_list = "lut_function"`
`write -f edif -hierarchy -o` <design name>`.edf`

Use the area report to determine the circuit area.

If you wish to maintain area report estimates as closely as possible during MAX+PLUS® II processing, Altera recommends that you select the WYSIWYG setting for the Global Project Synthesis Style in the Global Project Logic Synthesis dialog box (Assign menu). However, selecting the Normal or Fast style may yield a better result.

| For more information on how to use the FPGA Compiler software optimize your design for FLEX 8000 devices, refer to Chapter 5: Optimization for the Altera FLEX 8000 Architecture in the Synopsys FPGA Compiler User Guide.

| Go to FLEX Devices, which is available on the web, for additional information:

## Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In the MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project.

In designs targeted for the Synopsys Design Compiler and FPGA Compiler software, you can assign a limited subset of these resource assignments by setting attributes in the VHDL or Verilog HDL design files with the `set_attribute` command. These attributes are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File (.edf) into the ACF format. For information on making MAX+PLUS II-compatible resource assignments with the `set_attribute` command, go to the following topics:

- Assigning Pins, Logic Cells, & Chips
- Assigning Cliques
- Assigning Logic Options

You can also modify the ACF for a design to contain timing requirements and other assignments, as described in the following topics:

- Modifying the Assignment & Configuration File with the setacf utility
- Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
- Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities

|  | Refer to the following sources for related information:

- Synopsys documentation for additional information on how to assign properties
- "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Synopsys
- "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu), for information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF

## Assigning Pins, Logic Cells & Chips

You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device.

You can assign a signal to a particular pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. If you wish to set and maintain the performance of your project, assigning logic to a specific logic cell within a chip can minimize timing delays. In a project that is partitioned among multiple devices, you can assign logic functions that must be kept together in the same device to a chip. Chip assignments allow you to split a project so that only a minimum number of signals travel between devices, and to ensure that no unnecessary device-to-device delays exist on critical timing paths. You can assign a chip to a device in MAX+PLUS® II software.

To make pin, logic cell, and chip assignments, use the `set_attribute` command at a dc_shell prompt. Before using the `set_attribute` command, add the following line to your .synopsys_dc.setup file:

`edifout_write_properties_list` = {`LOGIC_OPTION, CLIQUE, CHIP_PIN_LC`}

Table 1 shows the syntax to use for chip, pin, and logic cell assignments:

Table 1. Commands for Chip, Pin, & Logic Cell Assignments
Assignment Type | Command to Type Note (1)
Chip | `set_attribute find (`<design object>`, (`<instance name>`)) "CHIP_PIN_LC" -type string "`<chip name>`"`
Pin | `set_attribute find (`<design object>`, (`<instance name>`)) "CHIP_PIN_LC" -type string "`<chip name>`@`<pin number>`"`
Logic cell number | `set_attribute find (`<design object>`, (`<instance name>`)) "CHIP_PIN_LC" -type string "`<chip name>`@LC`<logic cell number>`"`
I/O cell number | `set_attribute find (`<design object>`, (`<instance name>`)) "CHIP_PIN_LC" -type string "`<chip name>`@IOC`<I/O cell number>`"`
Embedded cell number | `set_attribute find (`<design object>`, (`<instance name>`)) "CHIP_PIN_LC" -type string "`<chip name>`@EC`<embedded cell number>`"`

Note:

1. In this table, <design object> represents ports, references, cells, nets, or pins.

Examples:

`set_attribute find (cell, (U1)) "CHIP_PIN_LC" -type string "chip1"`

`set_attribute find (cell, (U1)) "CHIP_PIN_LC" -type string "chip1@K2"`

`set_attribute find (cell, (U1)) "CHIP_PIN_LC" -type string "chip1@LC44"`

| Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software.

## Assigning Cliques

You can define a group of logic functions as a single, named unit, called a clique. The MAX+PLUS® II Compiler attempts to place all logic in the clique in the same logic array block (LAB) to ensure optimum speed. If the project does not use multi-LAB devices, or if it is not possible to fit all clique members into a single LAB, the clique assignment ensures that all members of a clique are placed in the same device. In FLEX® 6000, FLEX 8000, MAX® 9000, and FLEX 10K devices, the Compiler also attempts to place the logic in LABs in the same row. Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, and to ensure that no unnecessary LAB-to-LAB or device-to-device delays exist on critical timing paths.

To make pin, logic cell, and chip assignments, use the `set_attribute` command at a dc_shell prompt. Before using the `set_attribute` command, add the following line to your .synopsys_dc.setup file:

`edifout_write_properties_list` = {`LOGIC_OPTION, CLIQUE, CHIP_PIN_LC`}

| To assign a clique, type the following command at a dc_shell prompt:
| `set_attribute find(`<design object>`,(`<instance name>`))``"CLIQUE" -type string "`<clique name>`"`
| For example: `set_attribute find (cell, (U1)) "CLIQUE" -type string "fast1"`

| Go to the following topics in MAX+PLUS II Help for related information:

- Assigning a Clique
- Guidelines for Achieving Maximum Speed Performance

## Assigning Logic Options

Logic options and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS® II Compiler also uses a device family-specific default logic synthesis style for each project.

To make pin, logic cell, and chip assignments, use the `set_attribute` command at a dc_shell prompt. Before using the `set_attribute` command, add the following line to your .synopsys_dc.setup file:

`edifout_write_properties_list` = {`LOGIC_OPTION, CLIQUE, CHIP_PIN_LC`}

| To assign a logic option or a logic synthesis style, type the following command at a dc_shell prompt:
| `set_attribute find(`<design object>`, (`<instance name>`)) "LOGIC_OPTION" -type string "`<logic option>`=`<value>`"`
| For example:
| `set_attribute find (cell, (U1)) "LOGIC_OPTION" -type string "STYLE=FAST"`
| To specify multiple logic options, use commas as separators.
| For example:
| `set_attribute find (cell, (U1))"LOGIC_OPTION" -type string "STYLE=FAST, CARRY_CHAIN=MANUAL"`

|  | Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments.

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility

Altera provides the syn2acf utility, which is an interface program that converts Synopsys timing constraints from non-hierarchical designs into the MAX+PLUS® II Assignment & Configuration File (.acf) format. For information on converting timing constraints from hierarchical designs, refer to Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities.

The syn2acf utility requires the following input files:

- Flattened EDIF netlist file
- dc_shell script file
- Standard Delay Format (SDF) constraints construct
- SDF timing delay construct

To use the syn2acf utility, follow these steps:

1. Set the timing constraints by using one of the following methods:

   | Start the Synopsys Design Analyzer and specify timing constraints by choosing appropriate menu commands.

   or:

   | Create the <design name>.cmd file for use with a dc_shell script. See Figure 1.

| The syn2acf utility does not support `set_arrival` timing constraints for internal nodes.

Figure 1. Sample Command File (.cmd) for Setting Timing Constraints

    create_clock -period 50 -waveform {0 25} CLK
    set_clock_skew -delay 2 CLK
    set_input_delay 10 IN2
    set_input_delay 5 -clock CLK IN1
    set_output_delay 20 OUT2
    set_output_delay 5 -clock CLK OUT1
    set_max_delay 25 -to OUT1
    set_max_delay 35 -to OUT2
    set_multicycle_path 2 -to n20_reg

2. Compile the design and run the syn2acf utility either from the command line or with a Design Compiler dc script:

   | Compile the design, then type the following command from the UNIX prompt to start the syn2acf utility: `/usr/maxplus2/synopsys/bin/syn2acf` <design name>``

   or:

   | Run a dc script inside the dc_shell script that reads the VHDL design, compiles it, and runs the syn2acf utility. Figure 2 shows a sample dc script.

| The syn2acf utility uses the `ALT_HOME` environment variable, if it has been specified, to determine the MAX+PLUS II system directory; otherwise, it uses the /usr/maxplus2 directory. To specify a different MAX+PLUS II system directory with the `ALT_HOME` environment variable, you can either edit the .cshrc file to specify the correct directory or type the following command at the UNIX prompt:
`setenv ALT_HOME` <MAX+PLUS II system directory>

Figure 2. Sample Script for Running the syn2acf Utility

`/* dc_script example to interface with syn2acf */` |
`dc_shell <<!` |
`read -f vhdl` <design name>`.vhd`
`include` <design name>`.cmd` | `/*set timing constraints*/`
`compile`
`current_design=`<design name> |
`include /usr/maxplus2/synopsys/bin/syn2acf.cmd` | `/*generate required files*/`
`sh /usr/maxplus2/synopsys/bin/syn2acf` <design name> | `/*invoke syn2acf utility*/`
`quit` |
`!` |

| The syn2acf utility cannot support maximum Clock frequency (fMAX) correctly if more than one Clock skew is specified in the dc_shell command script. This problem occurs because the Synopsys `write_script` command drops the Clock skew information for the registers. The syn2acf utility will use the last Clock skew number to calculate fMAX.

The sample dc script includes the Altera®-provided syn2acf.cmd file, shown in Figure 3, to generate the required input files for the syn2acf utility.

Figure 3. Altera-Provided syn2acf.cmd File

    ungroup -flatten -all
    write -f edif
    write_script > altsyn.dc
    write_constraints -format sdf -cover_design
    write_timing -format sdf

All timing assignments generated by the syn2acf utility are written to the Timing Requirement Assignments Section of the project's ACF, with the assignment source identifier `{synopsys}` at the end of each line. Figure 4 shows a sample ACF excerpt that contains Synopsys timing constraints generated by the syn2acf utility.

Figure 4. Sample ACF Excerpt with Synopsys Timing Constraints

    TIMING_POINT
    BEGIN
       "|OUT2"    : TCO = 15.00ns {synopsys};
       "|IN1"     : TPD = 10.00ns {synopsys};
       "|IN2"     : TPD = 5.00ns {synopsys};
       "|OUT1"    : TCO = 20.00ns {synopsys};
       "|IN1"     : TSU = 20.00ns {synopsys};
       "|IN2"     : TSU = 117.00ns {synopsys};
       "|CLK"     : FREQUENCY = 50.00ns {synopsys};
       "|n10_reg" : FREQUENCY = 100.00ns {synopsys};
    END;

Altera provides sample files for these utilities in the /usr/maxplus2/synopsys/bin directory.

## Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities

Altera provides the gen_hacf and gen_iacf utilities, which convert Synopsys timing constraints into the MAX+PLUS® II Assignment & Configuration File (.acf) format. For information on converting timing constraints from non-hierarchical designs, refer to Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility. The gen_iacf utility generates intermediate, individual ACFs with the extension .iacf for each subdesign. The gen_hacf utility merges the individual .iacf files into a single ACF for the whole design.

To use the gen_iacf and gen_hacf utilities, follow these steps:

| You can create a dc_shell script that performs most of these steps. Refer to Figure 2 for a sample dc_shell script.

1. Make sure that you have specified the correct path of your local Perl executable, as specified in step 5 of Setting Up the MAX+PLUS II/Synopsys Working Environment.

   | The gen_iacf and gen_hacf utilities use the `ALT_HOME` environment variable, if it has been specified, to determine the MAX+PLUS II system directory; otherwise, it uses the /usr/maxplus2 directory. To specify a different MAX+PLUS II system directory with the `ALT_HOME` environment variable, you can either edit the .cshrc file to specify the correct directory or type the following command at the UNIX prompt:
   `setenv ALT_HOME` <MAX+PLUS II system directory>

2. Once you have synthesized your design with Design Compiler or FPGA Compiler, generate an hierarchical EDIF netlist file for the top-level design by typing the following command at the dc_shell prompt:

   `write -f edif -hierarchy` <top-level design name> `-o` <top-level design name>`.hier.edf`

3. Generate intermediate ACF files (.iacf) for all subdesigns that have constraints, including the top-level design.

   1. Generate the following input files for the gen_iacf utility by using a gen_iacf.cmd file. Figure 1 shows a sample gen_iacf.cmd file.

      - Flattened EDIF netlist file
      - dc_shell script file
      - Standard Delay Format (SDF) constraints construct
      - SDF timing delay construct

      | The gen_iacf and gen_hacf utilities do not support `set_arrival` timing constraints for internal nodes.

      Figure 1. Sample gen_iacf.cmd File

      `ungroup -flatten -all`
      `write -f edif`
      `write_script > <design_name> + "_setup.dc"`
      `write_constraints -format sdf -cover_design`
      `write_timing -format sdf`

      | This sample command file assumes that the `design_name` variable has been set before the command file is included.

   2. Run the gen_iacf utility for each design that has timing constraints (including the top-level design) by typing the following command at the UNIX prompt:

      `gen_iacf` <design name>

4. Rename the top-level hierarchichal EDIF netlist file to <top-level design name>.edf, if you have not already done so.

5. Use the gen_hacf utility to merge the .iacf files for the top-level design and subdesigns into a single hierarchical ACF file, called <top level design name>.acf. Type the following command at the dc_shell prompt to start the gen_hacf utility and merge the files:

   `gen_hacf` <top-level design name>`[`<sub-design file list>`]`

Figure 2 shows a sample dc_shell script, which includes all of the steps for using the gen_iacf and gen_hacf utilities.

Figure 2. Sample Script for Running the gen_iacf and gen_hacf Utilities

    /* Sample dc_shell script for converting hierarchical
    Synopsys timing constraints to the ACF format
    The example design TOP has 3 lower-level
    subdesigns - LOWER1, LOWER2, LOWER3.  Only
    LOWER1, LOWER2 and TOP designs have constraints. */

    link_library		= flex10k-3.db
    target_library		= flex10k-3.db
    synthetic_library	= flex10k-3.sldb

    read -f vhdl LOWER1.vhd
    read -f vhdl LOWER2.vhd
    read -f vhdl LOWER3.vhd
    read -f vhdl TOP.vhd

    elaborate LOWER1
    current_design=LOWER1

    /* Include user-defined timing constraints for LOWER1 */

    include timing1.cmd
    compile
    design_name=LOWER1

    /* generate input files for gen_iacf */

    include /usr/maxplus2/synopsys/bin/gen_iacf.cmd

    /* generate an intermediate ACF (.iacf) file for LOWER1 design */

    sh /usr/maxplus2/synopsys/bin/gen_iacf LOWER1

    elaborate LOWER2
    current_design=LOWER2

    /* Include user-defined timing constraints for LOWER2 */

    include timing2.cmd
    compile
    design_name=LOWER2

    /* generate input files for gen_iacf */

    include /usr/maxplus2/synopsys/bin/gen_iacf.cmd

    /* generate an intermediate ACF (.iacf) file for LOWER2 design */

    sh /usr/maxplus2/synopsys/bin/gen_iacf LOWER2

    elaborate TOP
    current_design=TOP

    /* Include user-defined timing constraints for TOP */

    include timing3.cmd
    compile

    /* generate a hierarchical EDIF netlist file for
    the top-level design before it is flattened by
    the gen_iacf.cmd utility */

    write -f edif -hierarchy TOP -o TOP.hier.edf

    design_name=TOP

    /* generate input files for gen_iacf */

    include /usr/maxplus2/synopsys/bin/gen_iacf.cmd

    /* generate an intermediate ACF (.iacf) file for design TOP */

    sh /usr/maxplus2/synopsys/bin/gen_iacf TOP

    /* Rename the hierarchical EDIF netlist file generated
    earlier to <top level design>.edf, which is required by
    gen_hacf utility and MAX+PLUS II */

    sh mv TOP.hier.edf TOP.edf

    /* Merge all .iacf files to generate the final top-level ACF
    File subdesign.list in the following command lists the names
    of subdesigns that have timing constraints, one per line.
    In this example it has 2 lines, one each for LOWER1 and LOWER2.
    Top-level design name should not be specified in this file. */

    sh /usr/maxplus2/synopsys/bin/gen_hacf TOP subdesign.list

    quit

| The gen_iacf utility cannot support maximum Clock frequency (fMAX) correctly if more than one Clock skew is specified in the dc_shell command script. This problem occurs because the Synopsys `write_script` command drops the Clock skew information for the registers. The gen_iacf utility will use the last Clock skew number to calculate fMAX.

All timing assignments generated by the gen_iacf utility are written to the Timing Requirement Assignments Section of the project's ACF, with the assignment source identifier `{synopsys}` at the end of each line. Figure 4 shows a sample ACF excerpt that contains Synopsys timing constraints generated by the gen_iacf utility.

Figure 4. Sample ACF Excerpt with Synopsys Timing Constraints

    TIMING_POINT
    BEGIN
       "|OUT2"    : TCO = 15.00ns {synopsys};
       "|IN1"     : TPD = 10.00ns {synopsys};
       "|IN2"     : TPD = 5.00ns {synopsys};
       "|OUT1"    : TCO = 20.00ns {synopsys};
       "|IN1"     : TSU = 20.00ns {synopsys};
       "|IN2"     : TSU = 117.00ns {synopsys};
       "|CLK"     : FREQUENCY = 50.00ns {synopsys};
       "|n10_reg" : FREQUENCY = 100.00ns {synopsys};
    END;

| The MAX+PLUS II Compiler flattens the design internally before compiling it, which may convert some of the ports on the sub-designs into internal or buried nodes. In addition, the gen_iacf and gen_hacf utilities will correctly pass tCO and tPD assignments made at lower levels of hierarchy to the ACF, but the MAX+PLUS II Compiler will ignore them and generate one or more warning messages (e.g., `Warning: Ignored timing assignment for tsu|tpd|tco on buried node |TIME_STATE_MACHING:U1|tb1_3:U115|:30`). In addition, hierarchical timing constraints may result in duplicate assignments in the ACF, and the MAX+PLUS II Compiler could generate an additional warning (e.g., `Warning: Ignored redefinition of resources assignment (logic option assignment) for node 'CLK' Processing . . .` ).

## Performing a Pre-Routing or Functional Simulation with VSS Software

After you have synthesized and optimized a VHDL or Verilog HDL design with the Design Compiler or FPGA Compiler software, you can perform a pre-routing or functional simulation with the Synopsys VHDL System Simulator (VSS) software.

To perform a pre-routing/functional simulation, follow these steps:

1. Be sure to set up the working environment correctly, as described in the following topics:
   - Setting Up the MAX+PLUS II/Synopsys Working Environment
   - Setting Up Design Compiler & FPGA Compiler Configuration Files
   - Setting Up the DesignWare Interface
   - Setting Up VSS Configuration Files

2. Create a VHDL or Verilog HDL design file that follows the guidelines described in one of the following topics:
   - Creating VHDL Designs for Use with MAX+PLUS II Software
   - Creating Verilog HDL Designs for Use with MAX+PLUS II Software

3. Synthesize and optimize your design with the Design Compiler or FPGA Compiler, as described in Synthesizing & Optimizing VHDL & Verilog HDL Files with Design Compiler or FPGA Compiler Software.
4. Save your design as a VHDL Design File (.vhd).

   | VSS requires each architecture/entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis.

5. Use VSS and one of the Altera pre-routing functional simulation libraries to simulate the design.

6. When you are ready to compile your project with MAX+PLUS II software, save the design as an EDIF netlist file (.edf), then process it as described in Compiling Projects with MAX+PLUS II Software.

| Refer to the following sources for related information:

- VHDL System Simulator Core Programs Manual for more information about VSS
- Performing a Timing Simulation with VSS Software

## Resynthesizing a Design Using the alt_vtl Library & a MAX+PLUS II SDF Output File

Altera provides the alt_vtl.db post-synthesis library for technology mapping or resynthesis. You can use this library with the MAX+PLUS® II-generated Standard Delay Format (SDF) Output File (.sdo) to retarget and resynthesize your design for another device family by performing the following steps:

To retarget and resynthsize a design, follow these steps:

1. Generate an EDIF Output File (.edo) and an SDF Output File (.sdo), as described in Compiling Projects with MAX+PLUS II Software.

2. Modify your .synopsys_dc.setup file to include the following lines: `search_path = {./usr/maxplus2/synopsys/library/alt_post/syn/lib
   `<target library path>`};
   target_library = {`<target library path>`};
   symbol_library = {`<target library symbol file>`};
   link_library = {alt_vtl.db};
   `

3. In the Design Compiler or FPGA Compiler software, type the following commands to read in the EDIF and SDF output files: `read -f edif` <design name>`.edo
   read_timing -load_delay net` <design name>`.sdo`

4. Type the following commands to compile your design, report the timing information, and create an EDIF netlist file (.edf) that can be processed with the MAX+PLUS II Compiler. `compile
   report_timing
   write -f edif -hierarchy -o` <design name>`.edf`

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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