// MAX+plus II Verilog Example
// Component Instantiation Statement
// Copyright (c) 1997 Altera Corporation

module compinst (data, clock, clearn, presetn, a, b,                 
		 c, gn, d, q_out, y, wn,);


    input   data, clock, clearn, presetn, a, b, c, gn; 
    input   [7:0] d;
    output  q_out, y, wn;

    DFF dff1 (.d (data), .q (q_out), .clk (clock), .clrn (clearn), .prn (presetn));

    \74151b mux (c, b, a, d, gn, y, wn);

endmodule

