## Performing Timing Verification of EDIF Output Files (.edo) with MOTIVE & MOTIVE for Powerview Software

After you have compiled a project and generated an EDIF Output File (.edo) with the MAX+PLUS® II software, you can use Viewlogic MOTIVE or MOTIVE for Powerview software to perform timing verification. The max2_MOTIVE tool is located in both the Altera® Toolbox Design Tools Drawer and the Altera Toolbox Max2 Express Drawer. The MOTIVE timing model library, motive.lib, provides models of basic primitives and the `clklock` megafunction for timing verification.

To perform timing verification for EDIF Output Files with MOTIVE or MOTIVE for Powerview software, follow these steps:

1. Set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Generate an EDIF Output File (.edo) by compiling your design with the MAX+PLUS II software, as described in Compiling Projects with MAX+PLUS II Software.

3. Start the MOTIVE for Powerview software by double-clicking Button 1 on the max2_MOTIVE icon in the Altera Toolbox Design Tools Drawer. The MOTIVE for Powerview Control Panel opens.

4. Choose Setup Environment (File menu) to open the Environment Parameters dialog box, and specify the following options:

   1. Specify the directory for the Project Directory option.

   2. Specify /usr/maxplus2/vwlogic/library/alt_time/motive.lib for the Model Library Search Path option.

   3. Select EDIF for the Netlist Input Format option.

   4. Choose Accept. The MOTIVE for Powerview software automatically creates a tim subdirectory, which contains MOTIVE design cases and related files, in the current working directory.

5. Choose Save Parameters (File menu) to save your customized project setup.

6. To specify the project name, choose the New Design button to open the Adding a New Design dialog box. Type the design name in the New Design box. Choose Accept, then Dismiss.

7. To specify the case name, choose the New Case button to open the Adding a New Case dialog box. Type the case name in the New Case box. Select Default as the New Case Type. Choose Accept, then Dismiss.

8. Choose Browse Cases (File menu) to open the Case Display dialog box. In the Case Display dialog box, double-click Button 1 on the field that contains the case for the project. Double-clicking on the field opens a file manager listing all the project files located under that case. Choose Dismiss in the Case Display dialog box.

   1. Choose the Get File button from the file manager to display the Get File box at the bottom of the window. This box allows you to specify which file(s) you would like to add to the list of files for the current case.

   2. Type /<working directory>/<project name>`.edo` in the Get File box and choose Copy. The new file appears in the list of design files.

   3. Type /<working directory>/<project name>`.sdo` in the Get File box and choose Copy.

   4. Type /<working directory>/<project name>`.ref` in the Get File box and choose Copy.

   5. If your project contains memory functions, such as `ram`, `rom`, `dpram`, `scfifo`, `dcfifo`, `altdpram`, or `clklock`, type <project name>.vmo in the Get File box and choose Copy to add the MAX+PLUS II-generated VHDL Memory Model Output File (.vmo) to the list of files for the case. The MAX+PLUS II Compiler automatically generates this file for a project that contains memory functions.

      | Every MOTIVE analysis requires a MOTIVE Clock Reference File (.ref). If the project is simple, you can create the file in the Setup Advisor. Otherwise, you must create the file in a text editor using MOTIVE syntax. For more information on the purpose, function, and syntax of MOTIVE Clock Reference Files, see the MOTIVE System Reference.

   6. Choose Dismiss.

9. Choose the Netlister button in the MOTIVE for Powerview Control Panel to open the EDIF Netlist Parameters dialog box. To create a FutureNet Format Netlist File (.pin) with the EEDIF Netlister for your design, follow these steps:

   1. Choose the Select Design button to open the Select Design dialog box.

   2. Double-click Button 1 on the project name to open the Select Case dialog box.

   3. Double-click Button 1 on the case name in the Select Case dialog box to open the Select File dialog box.

   4. Double-click Button 1 on the EDIF Output File, <project name>.edo, in the Select File dialog box.

   5. Select Keep for all Case Sensitivity options in the EDIF Netlist Parameters dialog box.

   6. Choose Accept, then Dismiss to close the EDIF Netlist Parameters dialog box.

10. Choose the SDF2MTV button in the Control Panel to open the SDF2MTV (MOTIVE SDF Reader) Parameters dialog box and specify the following options:

    1. Choose the Select button next to the SDF Filename box to open the Select File dialog box.

    2. Double-click Button 1 on the project's Standard Delay Format (SDF) Output File, <project name>.sdo, in the Select File dialog box. The SDF2MTV utility creates a MOTIVE Model Pre-Processor (MMP) Control File (.ctl) that allows you to annotate the parameterized library, and an Interconnect Delay Data File (.idd).

    3. Choose Accept, then Dismiss to close the Select File dialog box.

11. If your project contains `ram`, `rom`, `dpram`, `scfifo`, `dcfifo`, `altdpram`, or `clklock` megafunctions, use the genmtv utility to back-annotate the MMP Control File and to allow the MMP Control File to recognize the function. The input to the genmtv utility is the VHDL Memory Model Output File (.vmo) described above. From the /<working directory>/<project name>/<case name> directory, type the following command at the UNIX prompt:

    `genmtv` <project name>

12. If your project contains RAM or ROM functions and you turned on the Flatten Bus option in the MAX+PLUS II Compiler's EDIF Netlist Writer Settings dialog box when you compiled your project, you must edit the mem.lib file, i.e., the MOTIVE Model Pre-Processor timing library file created with the genmtv utility. You must remove bracket `[` `]` characters from all occurrences of the address bus, e.g., change `A[0]` to `A0`, in both the `INPUTS` and `MIXED` sections of every RAM and ROM cell definition in mem.lib.

13. Choose the MMP button from the Control Panel to open the MOTIVE Model Pre-processor (MMP) Parameters dialog box and specify the following options:

    1. Choose the Select button next to the MMP Ctl File box to open the Select File dialog box.

    2. Double-click Button 1 on the project's MMP Control File, <project name>.ctl, in the Select File dialog box.

    3. In the MOTIVE Model Pre-processor (MMP) Parameters dialog box, choose the Setup Model Libraries button to display boxes on the right side of the dialog box that allow you to list additional source model libraries. In one of these boxes, type the following path and filename:

       `/usr/maxplus2/vwlogic/library/alt_time/motive.drv`

    4. If your project contains RAM or ROM functions, repeat step 13c but specify the pathname of the mem.lib file created in step 12. For example:

       `/usr/maxplus2/`<working directory>`/..../`<case name>`/mem.lib`

    5. In the MOTIVE Model Pre-processor (MMP) Parameters dialog box, choose Accept, then Dismiss. The MMP utility creates a design-specific Timing Model Library File (.mod).

14. Choose the Analyze button from the Control Panel to expand the Control Panel.

15. Double-click Button 1 on the project name in the Select Design box in the Control Panel to open the Select Case box.

16. Select the specific case of the project in the Select Case box and double-click Button 1 on the case name to open MOTIVE software and its Setup Advisor. The Setup Advisor helps guide you through the following steps to set up and configure a case analysis:

    1. In the Setup Advisor window, choose the Continue button to open the Project Name Selection dialog box, which displays the project name.

    2. Choose the Begin analysis button to open the Checking for existing project dialog box.

    3. Choose Continue to open the Design Specific Flow(s) dialog box and set up the project through the Setup Advisor. The Design Name option lists the project filename.

    4. Choose Continue to open the Flow and Translation Selection dialog box.

    5. Select the Manual Translation Flow option to specify input files and the steps to perform in the timing verification flow for MOTIVE software. Choose Continue to open the Manual Flow Selection dialog box and specify the following options:

       Option: | Setting:
       Netlist/Pinlist | FutureNet (.pin)
       Parametric | OVI Verilog (.sdf)

       In the Other box, select Use available MOTIVE files to use the input files you created in previous steps. Choose Continue to open the FutureNet Pinlist Preparation dialog box.

    6. Type the project name in the Root Block box. Choose Continue to open the OVI Standard Parametric Back-annotation dialog box.

    7. Type <project name>.sdo in the OVI (SDF) back-annotation file box. Choose Continue to open the MOTIVE Model Compilation dialog box.

    8. Replace the entry in the Control file(s) box with <project name>`.ctl`. Type the following two filenames, which must be separated by a space, in the Libraries(s) box:

       `/usr/maxplus2/vwlogic/library/alt_time/motive.lib /usr/maxplus2/vwlogic/library/alt_time/motive.drv`

    9. If your project contains RAM or ROM functions, add the mem.lib file to the directories specified in step 16h.

    10. Choose Continue to open the Quick Definition of Existing MOTIVE Files dialog box. The <project name>.ref filename appears in the Clock Reference File (.ref) box.

    11. Replace the entry in the Design's (pre-compiled) Model File (.mod) box with <project name>.mod. Choose Continue to open the Congratulations dialog box.

    12. Choose Continue to open the Cleaning up dialog box after completing the Setup Advisor interview. Select Save under Project name to save your setup, and choose Continue to close the Setup Advisor window.

17. In the MOTIVE window, choose Verify (Analyze menu) and then choose Execute to start verification. To view the output files, choose Output Files (View menu).

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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