## Resynthesizing a Design Using the alt_vtl Library & a MAX+PLUS II SDF Output File

Altera provides the alt_vtl.db post-synthesis library for technology mapping or resynthesis. You can use this library with the MAX+PLUS® II-generated Standard Delay Format (SDF) Output File (.sdo) to retarget and resynthesize your design for another device family by performing the following steps:

To retarget and resynthsize a design, follow these steps:

1. Generate an EDIF Output File (.edo) and an SDF Output File (.sdo), as described in Compiling Projects with MAX+PLUS II Software.

2. Modify your .synopsys_dc.setup file to include the following lines: `search_path = {./usr/maxplus2/synopsys/library/alt_post/syn/lib
   `<target library path>`};
   target_library = {`<target library path>`};
   symbol_library = {`<target library symbol file>`};
   link_library = {alt_vtl.db};
   `

3. In the Design Compiler or FPGA Compiler software, type the following commands to read in the EDIF and SDF output files: `read -f edif` <design name>`.edo
   read_timing -load_delay net` <design name>`.sdo`

4. Type the following commands to compile your design, report the timing information, and create an EDIF netlist file (.edf) that can be processed with the MAX+PLUS II Compiler. `compile
   report_timing
   write -f edif -hierarchy -o` <design name>`.edf`

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Design Compiler & FPGA Compiler Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.