## Creating Concept Schematics for Use with MAX+PLUS II Software

You can create Concept schematics and convert them to EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler. To create a Concept schematic for use with the MAX+PLUS II software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Make sure the required directive files are in the /<working directory>/<design name>/source directory. If not, you can use the Altera-provided template files located in the following directories:

   - /usr/maxplus2/simlib/concept/edifnet/templates
   - /usr/maxplus2/simlib/concept/edifnet/redifnet

3. Start the Concept schematic editor by typing `concept` <design name> at a UNIX prompt from the /<working directory>/source directory. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to Concept & RapidSIM Local Work Area Directory Structure for more information on directories in Concept.

4. To write a Verilog HDL text file whenever the design is saved, choose the Block button in the Concept window.

   | To use the HDL Direct utility to process your design, turn on the HDL Direct On option in the Concept window. Go to Concept & HDL Direct Project Directory Structure for information on the files generated by Concept software when using the HDL Direct utility.

5. Enter primitives, megafunctions, and macrofunctions from the following Altera-provided component libraries:
   - alt_max2 includes macrofunctions, megafunctions, and primitives.
   - alt_lpm includes library of parameterized modules (LPM) functions (available only if you use HDL Direct software).

   See the following topics for instructions for specific functions:

   - Instantiating LPM & Other Parameterized Functions in Concept Schematics
   - Instantiating the clklock Megafunction in Concept Schematics

   | You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

6. If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera® Hardware Description Language (AHDL) Text Design Files, go to Creating Hierarchical Projects in Concept Schematics.

7. Enter meaningful instance names for all symbols and functions so that you can easily trace internal node names during simulation and debugging operations. For example, if an `a161` macrofunction is instantiated several times in one design, you should define a unique name for each instance. The instance name for each symbol is controlled by `INST` property. For more information on assigning properties, refer to the Cadence Concept Schematic User Guide.

8. Enter input, output, and bidirectional ports:

   - If you turned on the HDL Direct On option in step 4, add `inport` and `outport` symbols from the hdl_direct_lib library to the interface symbols.

   - If you are not using HDL Direct, use `flag` symbols from the standard library to indicate input, output, and bidirectional ports. Be sure to end pin names with `\I` to identify them as interface signals.

   | If a pin is not used, leave it floating. The concept2alt utility removes all unconnected pins when it generates an EDIF netlist file.

9. (Optional) To enter resource assignments in your Concept schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.

10. (Optional) Perform a functional simulation, as described in one of the following topics:
    - Performing a Functional Simulation of a Concept Schematic with the hdlconfig Utility & Verilog-XL Software
    - Performing a Functional Simulation of a Concept Schematic with VerilogLink & Verilog-XL Software

11. Use the concept2alt utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Concept Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the concept2alt utility.

12. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept schematic files:

- /usr/maxplus2/examples/cadence/example1/fulladd
- /usr/maxplus2/examples/cadence/example4/fulladd2
- /usr/maxplus2/examples/cadence/example6/fa2
- /usr/maxplus2/examples/cadence/example12/fifo

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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