## Preparing EDIF Output Files for Timing Simulation with Logic Modeling SmartModel Software

Once you have generated an EDIF Output File (.edo) for a design with the MAX+PLUS® II Compiler, you can use Logic Modeling SmartModel software to prepare it for simulation.

To use Logic Modeling SmartModel software, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Generate an EDIF Output File for your project, as described in Compiling Projects with MAX+PLUS II Software.

3. In the Navigator window, select your project's icon, press Button 3, and choose Open max2_lmi to start the Logic Modeling EDIF2SCF compiler and create a SmartModel Configuration Format File, as described in Creating a Logic Modeling SmartModel Configuration Format File.

4. Create a schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software, that contains an instance of a Logic Modeling SmartModel for the Altera® device specified in your project:

1. Start Design Architect by double-clicking on your project's icon in the Design Manager tools window.

2. Choose Altera Libraries (Libraries menu) and choose LOGIC MODELING (Altera Libraries menu). Select the appropriate device model for the Altera device specified in your project.

3. Change the `PLDFILE` property for the Altera device model to the full pathname of the SmartModel Configuration Format File generated in step 2.

4. Add pins to the device model.
5. Check and save the schematic in your project directory.

5. Select the icon for the folder representing the schematic generated in step 3, press Button 3, and choose Open max2_lve to open DVE and prepare your EDIF Output File for QuickSim II timing simulation. DVE generates a viewpoint named altera_lsim.

6. Select the icon for the folder representing the schematic generated in steps 2a through 2e, press Button 3, and perform a timing simulation on your project, as described in steps 5 and 6 of Performing a Timing Simulation with DVE & QuickSim II Software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Mentor Graphics/Exemplar Logic Topics | QuickSim II Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.