## Creating AHDL Designs for Use with MAX+PLUS II Software

The Altera® Hardware Description Language (AHDL) is a high-level language that supports design entry with Boolean equations, conditional logic, truth tables, arithmetic operators, and parameterized functions, including Library of Parameterized Modules (LPM) functions. AHDL provides a compact and efficient syntax for state machines, decoders, and comparators. The MAX+PLUS® II software can read and compile AHDL Text Design Files (.tdf) directly.

| AHDL TDFs must be in ASCII file format. If you enter a file with a word processor, you must save it in text-only format. For complete information on AHDL, refer to MAX+PLUS II Help.

You can also use AHDL TDFs to combine EDIF netlist files generated from ViewDraw schematics with other design files to create complex, hierarchical circuits.

| AHDL templates are available with the MAX+PLUS II Text Editor's AHDL Template command (Templates menu) or in the ASCII ahdl.tap file, which is located in the /usr/maxplus2 directory. Go to "Inserting an AHDL Template" in MAX+PLUS II Help for information on using templates in the Text Editor.

Installing the Altera-provided MAX+PLUS II/Viewlogic interface on your computer automatically creates the following sample AHDL design files:

- /usr/maxplus2/examples/Viewlogic/example2/decode.tdf
- /usr/maxplus2/examples/Viewlogic/example3/fadd2

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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