## Performing a Functional Simulation with QuickHDL Software

You can use Mentor Graphics QuickHDL software to functionally simulate VHDL or Verilog HDL design files before compiling them with the MAX+PLUS® II Compiler.

| If you wish to functionally simulate a hierarchical design that uses multiple design entry methods, you should use QuickHDL Pro rather than QuickHDL. Refer to Performing a Functional Simulation with QuickHDL Pro Software for more information.

To functionally simulate a VHDL or Verilog HDL design, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design file that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Start Design Architect by double-clicking Button 1 on the max_da icon in the Design Manager tools window. You can also start Design Architect software by typing `max2_da` at the UNIX prompt.

4. Choose Lib (QuickHDL menu) and specify your work library name as the Work Library name. Choose OK.

5. Choose Map (QuickHDL menu) to map the instantiated function to the equivalent function in the Altera logic function library. Choose Set to specify altera as the Logical Name and $MAX2_MFLIB as the Physical Name. Choose OK.

6. Choose Compile (QuickHDL menu) and use the Navigator window to select the icon for your project. Specify your work library name as the Work Library name and select the Simulation setting in the Set VHDL Compilation Options or Set Verilog HDL Compilation Options window. Choose OK to compile.

7. Choose Simulate (QuickHDL menu) and specify your work library name as the Work Library name. Choose OK to start the QuickHDL Startup window.

8. Select the icon for your project in the Entity Configuration window and choose OK to simulate the design.

9. Synthesize and optimize the design, as described in Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software or Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software.

If your Verilog HDL design uses memory functions (RAM or ROM) that can be initialized with a hexadecimal file (Intel-format) initialization, you must convert these files into Verilog HDL format using the Programming Language Interface (PLI). To use the Altera-provided source code for PLI, perform the following steps:

1. Download the file http://www.edif.org/lpmweb/convert_hex2ver.c to your project directory.

2. Copy the following two files from the $MGC_HOME/shared/pkgs/quickhdl/include directory into the /usr/maxplus2 directory:

- $MGC_HOME/shared/pkgs/quickhdl/include/veriuser
- $MGC_HOME/shared/pkgs/quickhdl/include/acc_user

Refer to the Mentor Graphics QuickHDL User's Reference Manual, version 8.5-4.6i, for information on compiling the PLI application on different platforms and using the Verilog HDL PLI.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Performing a Timing Simulation with QuickHDL Software
- Performing a Functional Simulation with QuickHDL Pro Software

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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