## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Synopsys Software

The MAX+PLUS® II Compiler can process a VHDL or Verilog HDL file that has been synthesized by the Synopsys Design Compiler or FPGA Compiler software, saved as an EDIF 2 0 0 or 3 0 0 netlist file, and imported into the MAX+PLUS II software. The procedure below explains how to run Synopsys tools separately from MAX+PLUS II Software.

| You can also run Synopsys tools from within the MAX+PLUS II software to automatically generate and import an EDIF file. Refer to Running Synopsys Compilers from MAX+PLUS II Software for more information. In addition, if your MAX+PLUS II development system includes VHDL or Verilog HDL synthesis support, the MAX+PLUS II Compiler can directly synthesize VHDL or Verilog HDL logic. For more information, go to MAX+PLUS II VHDL or Verilog HDL Help.

The following steps explain how to synthesize and optimize a VHDL or Verilog HDL design for use with MAX+PLUS II software:

1. Be sure to set up your design environment correctly. This step includes specifying the target device family for the design. See the following topics:
   - Setting Up the Synopsys/MAX+PLUS II Working Environment
   - Setting Up the Design Compiler and FPGA Compiler Configuration Files
   - Setting Up the DesignWare Interface
   - Setting Up the VSS Configuration Files

2. Create a VHDL file, <design name>.vhd, or a Verilog HDL design, <design name>.v, using the MAX+PLUS II Text Editor or another standard text editor and save it in a project directory under your login directory. See the following topics for instructions:
   - Creating VHDL Designs for Use with MAX+PLUS II Software.
   - Creating Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Start the Design Compiler or FPGA Compiler software by typing either `dc_shell` or `fpga_shell` at the command line, respectively. To work within the graphical user interface, type `design_analyzer` for either tool.

4. Analyze and then compile the design with the Design Compiler, FPGA Compiler, or Design Analyzer software. The VHDL Compiler or HDL Compiler for Verilog software automatically translates the design into Synopsys database (.db) format. Specific steps are necessary for some types of projects before you process the design:

   1. If your FLEX 10K design includes RAM or ROM functions, follow these steps:

      1. (VHDL designs only) Because the VHDL Compiler software does not support the data type `string` for the Generic Clause, you must also enter the following command at the `dc_shell` prompt before you read the design:

         `hdlin_translate_off_skip_text=true`

      2. The timing model (.lib) generated by the genmem utility contains pin-to-pin delay information that can be used by the Synopsys Design Compiler and FPGA Compiler software. You must add this timing model to the existing library so that the compiler can access the timing information. Type the following commands at the dc_shell prompt:

         `read -f db flex10k`[<speed grade>]`.db` `update_lib flex10k`[<speed grade>] <RAM/ROM function name>`.lib`

      3. (Optional) Enter the following command to update your flex10k[<speed grade>].db file with the RAM/ROM timing information:

         `write_lib flex10k`[<speed grade>]`-o flex10k.db`

      See Instantiating RAM & ROM Functions in VHDL or Instantiating RAM & ROM functions in Verilog HDL for additional information.

   2. If you wish to allow the FPGA Compiler to perform N-input look-up table (LUT) optimization for a FLEX 6000, FLEX 8000, or FLEX 10K design, enter the following command at the `dc_shell` prompt before compiling the design:

      `edifout_write_properties_list = "lut function"`

      Go to Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000, or FLEX 10K Devices for more information.

   3. If you wish to enter resource assignments, go to Entering Resource Assignments.

   4. If you wish to direct the Design Compiler or FPGA Compiler to use sum-of-products logic in processing a MAX 7000 or MAX 9000 design, type the following commands at the `dc_shell` prompt before compiling the design:

      `set_structure false`
      `set_flatten -effort low`

      See MAX 7000 & MAX 9000 Synthesis Example for more information.

      For additional information on how the Design Compiler and FPGA Compiler synthesize and optimize a design, see the following topics:

      - Synopsys Design Compiler Reference Manual or Design Analyzer Reference Manual
      - DesignWare FLEX 8000 Synthesis Example

5. (Optional) View the optimized project with the Design Analyzer. The Design Analyzer uses the altera.sdb library to display optimized projects generated by the Design Compiler or FPGA Compiler.

6. (Optional) To view Synopsys-generated timing information and generate a file detailing primitive usage, type the following commands:

   `report_timing`
   `report_reference > <filename>```

7. (Optional) To functionally verify the project prior to processing with the MAX+PLUS II software, save the design as a VHDL netlist file, and simulate it as described in Performing a Pre-Routing or Functional Simulation with VSS Software.

8. Save the optimized project as an EDIF netlist file with the extension .edf.

9. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with the MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Synopsys interface on your computer automatically creates the following sample VHDL and Verilog HDL files:

- /usr/maxplus2/synopsys/examples/ministate.vhd
- /usr/maxplus2/synopsys/examples/ministate.v

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Resynthesizing a Design Using the alt_vtl Library and a MAX+PLUS II SDF Output File
- Programming Altera Devices

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Design Compiler & FPGA Compiler Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.