## Using Exemplar Logic Leonardo & MAX+PLUS II Software

The following topic describes how to use the Exemplar Logic Leonardo software with MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

- Software Requirements
- Altera-Provided Logic & Symbol Libraries
- Local Work Area Directory Structure
- Mentor Graphics Project Directory Structure
- MAX+PLUS II Project Directory Structure
- MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

### Design Entry

- Design Entry Flow
- Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software
- Performing a Functional Simulation with QuickHDL Pro Software

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Programming Altera Devices

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Exemplar Logic web site (http://www.exemplar.com)
- Mentor Graphics web site (http://www.mentor.com)

## Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

To use the MAX+PLUS® II software with Mentor Graphics/Exemplar Logic software, you must install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Mentor Graphics/Exemplar Logic interface is installed automatically when you install the MAX+PLUS II software on your computer.

Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization for information about the MAX+PLUS II/Mentor Graphics directories that are created during MAX+PLUS II installation.

| The information presented here assumes that you are using a C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Mentor Graphics interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Mentor Graphics software versions described in MAX+PLUS II/Mentor Graphics Software Requirements.

2. Add the following environment variables to your .cshrc file:

| `setenv ALT_HOME /usr/maxplus2`
| `setenv MGC_WD` <user-specified working directory>
| `setenv MGC_HOME` <Mentor Graphics system directory>
| `setenv MAX2_MENTOR /usr/maxplus2/mentor/max2`
| `setenv MGC_LOCATION_MAP` <user-specified location_map file>
| `setenv EXEMPLAR` <Galileo or Leonardo system directory>

| Installing the Altera®provided MAX+PLUS II/Mentor Graphics interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/.cshrc file.

3. Add the $MGC_HOME/bin, $MAX2_MENTOR/bin, $ALT_HOME/bin, $EXEMPLAR/bin/<os>, and $ALT_HOME/bin directories to the `PATH` environment variable in your .cshrc file, where <os> is the operating system, e.g., `SUN4` for SunOS; `SUN5` for Solaris.

4. If you plan to use the Altera Schematic Express (sch_exprss) utility or the Altera VHDL Express (vhd_exprss) utility, add the following environment variable to your .cshrc file:

| `setenv MAX2_QSIM /usr/maxplus2/simlib/mentor/max2sim`

5. Type `source ~/.cshrc` at a UNIX prompt to source the .cshrc file and validate the settings in steps 1 through 4.

6. Add the following lines to your MGC_location_map file:

| `$MAX2_MENTOR`
| `/usr/maxplus2/mentor/max2`
| `$MGC_GENLIB`
| `/`<user-specified Mentor Graphics GEN_LIB directory>
| `$MGC_LSLIB`
| `/`<user-specified Mentor Graphics LS_LIB directory>
| `$MAX2_EXAMPLES`
| `/`<user-specified example directory>
| `$MAX2_LMCLIB`
| `/`<user-specified Logic Modeling directory>
| `$MAX2_GENLIB`
| `/usr/maxplus2/simlib/mentor/alt_max2`
| `$MAX2_QSIM`
| `/usr/maxplus2/simlib/mentor/max2sim`
| `$MAX2_FONT`
| `/usr/maxplus2/mentor/max2/fonts`
| `$MGC_SYS1076_STD`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/ std`
| `$MGC_SYS1076_ARITHMETIC`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/arithmetic`
| `$MGC_SYS1076_PORTABLE`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/mgc_portable`
| `$MGC_SYS1076_IEEE`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/ieee`
| `$MGC_SYS1076_SRC`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/` src
| `$MAX2_MFLIB`
| `/usr/maxplus2/simlib/mentor/alt_mf`

| Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/location_map/location_map file.

7. If you want to use QuickHDL software to simulate VHDL or Verilog HDL designs, add the following line in the `[library]` section of your quickhdl.ini file: `altera = $MAX2_MFLIB`.

8. If you plan to use QuickHDL software to simulate VITAL-compliant VHDL files, add the following lines to your MGC_location_map file:

| `$MAX2_VTLLIB`
| `/usr/maxplus2/simlib/mentor/alt_vtl`

9. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:

| `cp /usr/maxplus2/maxplus2.ini $HOME`
| `chmod u+w $HOME/maxplus2.ini`

| The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as Alteraprovided logic and symbol library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.
Normally, you do not have to edit your local copy of maxplus2.ini, because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Mentor Graphics Software Requirements

The following products are used to generate, process, synthesize, and verify a project with the MAX+PLUS® II software and Mentor Graphics software:

Mentor Graphics | Exemplar | Altera
--- | --- | ---

version C.2:
System_1076 Compiler QuickSim II Design Architect ENRead ENWrite
GEN_LIB library
QuickHDL
QuickHDL Pro
QuickPath
LS_LIB library (optional)
DVE

Leonardo Spectrum version 2000.1b
MAX+PLUS II
version 10.0

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Mentor Graphics applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

## Altera-Provided Logic & Symbol Libraries

The MAX+PLUS® II/Mentor Graphics environment provides libraries for compiling, synthesizing, and simulating designs.

| You can create your own libraries of custom functions for use in Design Architect schematics and VHDL and Verilog HDL design files. You can use custom functions to incorporate an EDIF Input File (.edf), Text Design File (.tdf), or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the Altera®provided mnt8_bas.lmf and exemplar.lmf Library Mapping Files to map standard Design Architect symbols and VHDL and Verilog HDL functions to equivalent MAX+PLUS II logic functions. To use custom functions, you can create a custom LMF that maps your custom functions to the equivalent EDIF input file, TDF, or other design file. Go to "Library Mapping File" in MAX+PLUS II Help for more information.

### Design Architect Libraries

You can enter a Design Architect schematic with logic functions from these Altera-provided symbol libraries: ALTERA LPMLIB, ALTERA GENLIB, LSTTL BY TYPE, and LSTTL ALL PARTS. You can access these libraries by choosing Altera Libraries (Libraries menu) in the Design Architect software. For information on using library of parameterized modules (LPM) functions, see ALTERA LPMLIB Library below.

### ALTERA GENLIB Library (Design Architect) & Altera (VHDL) Libraries

The ALTERA GENLIB symbol library (called the Altera library for VHDL) includes several MAX+PLUS II primitives for controlling design synthesis and fitting. It also includes four macrofunctions (`8count`, `8mcomp`, `8fadd`, and `81mux`) that are optimized for different Altera device families, and the `clklock` phase-locked loop megafunction, which is supported for some FLEX® 10K devices.

The following table shows the MAX+PLUS II-specific logic functions.

Table 1. MAX+PLUS II-Specific Logic Functions
Macrofunctions Note (1) | Primitives
Name | Description | Name | Description | Name | Description
`8fadd` | 8-bit full adder | `LCELL` | Logic cell buffer | `EXP` | MAX® 5000, MAX 7000, and MAX 9000 Expander buffer
`8mcomp` | 8-bit magnitude comparator | `GLOBAL` | Global input buffer | `SOFT` | Soft buffer
`8count` | 8-bit up/down counter | `CASCADE` | FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer | `OPNDRN` | Open-drain buffer
`81mux` | 8-to-1 multiplexer | `CARRY` | FLEX 6000, FLEX 8000, and FLEX 10K carry buffer | `DFFE DFFE6K` Note (2) | D-type flipflop with Clock Enable
`clklock` | Phase-locked loop

Notes:

1. Logic function names that begin with a number must be preceded by "`a_`" in VHDL designs. For example, `8fadd` must be specified as `a_8fadd` instead.
2. If you want to use QuickHDL software, make sure you have updated your quickhdl.ini file, as described in step 7 of Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
3. For designs that are targeted for FLEX 6000 devices, you should use the `DFFE` primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the `DFFE6K` primitive.

| Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions.

### ALTERA LPMLIB Library

The Alteraprovided ALTERA LPMLIB library, which is available for Design Architect schematics and VHDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. The LPM standard defines a set of parameterized modules (i.e., parameterized functions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. After the design is completed, you can target the design to any device family. The parameters you specify for each LPM function determine which simulation models are generated.

| Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

## Local Work Area Directory Structure

Design Architect software automatically creates and maintains the project directory structure required for all stages of design entry. Galileo Extreme, Leonardo, and ENWrite software create a max2 subdirectory, if it does not already exist, under the project directory. These software applications also generate EDIF netlist files, and copy them from the <project name> directory to this max2 subdirectory. All MAX+PLUS® II Compiler output files are created in the max2 subdirectory.

Simulation files created with Mentor Graphics applications and Logic Modeling files are located in the board-level simulation subdirectory of the project directory. You can use these files during simulation with QuickSim II software.

The only directory you need to create is the local work directory, which should contain all project directories. Figure 1 shows the recommended file structure.

#### Figure 1. Recommended File Structure

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- MAX+PLUS II Project Directory Structure
- Mentor Graphics Project Directory Structure

## Mentor Graphics Project Directory Structure

Design Architect software generates the following files for each schematic:

- <drawing name>/mgc_component.attr
- <drawing name>/part.Eddm_part.attr
- <drawing name>/part.part_1
- <drawing name>/schematic.mgc_schematic.attr
- <drawing name>/schematic/schem_id
- <drawing name>/schematic/sheet1.mgc_sheet.attr
- <drawing name>/schematic/sheet1.sgfx_1
- <drawing name>/schematic/sheet1.ssht_1

The files generated for each schematic are stored in the schematic's <drawing name> directory and should not be edited. Mentor Graphics software automatically manages file storage and retrieval operations through this <drawing name> directory structure, which does not reflect hierarchical design relationships. Figure 1 shows a sample file structure with project1 as the UNIX project directory, and design1, subdesign1, and subdesign2 as the directories for the top-level design and subdesigns of the project.

Figure 1. Design Architect Project File Structure

When the ENWrite utility converts the schematic into an EDIF netlist file, it processes the design information and all related file subdirectories, then creates the EDIF netlist file in the directory defined by the user. The EDIF netlist file is named <project name>.edf, where <project name> is the name of the top-level design file. The <project name>.edf file is automatically moved to the max2 directory under the project directory.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Local Work Area Directory Structure
- MAX+PLUS II Project Directory Structure

## MAX+PLUS II Project Directory Structure

In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, VHDL, or Verilog HDL netlist file; an Altera Hardware Description Language (AHDL) Text Design File (TDF); or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by ENWrite, Galileo Extreme, or Leonardo software and imported into MAX+PLUS II as an EDIF Input File (.edf). Figure 1 shows an example of a MAX+PLUS II project directory.

Figure 1. Sample MAX+PLUS II Project Directory

The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Local Work Area Directory Structure
- Mentor Graphics Project Directory Structure

## MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

The following table shows the MAX+PLUS® II/Mentor Graphics interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation.

| For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

Table 1. MAX+PLUS II Directory Organization
Directory | Description
.lmf | Contains the Altera-provided Library Mapping Files, mnt8_bas.lmf and exemplar.lmf, that map Mentor Graphics and Exemplar Logic logic functions to equivalent MAX+PLUS II logic functions.
./mentor | Contains the AMPLE userware for the MAX+PLUS II/Mentor Graphics interface.
./simlib/mentor/alt_max2 | Contains MAX+PLUS II primitives such as `CARRY`, `CASCADE`, `EXP`, `GLOBAL`, `LCELL`, `SOFT`, `OPNDRN`, `DFFE`, and `DFFE6K` (D flipflop with Clock Enable) for use in Design Architect schematics.
./simlib/mentor/max2sim | Contains the MAX+PLUS II/Mentor Graphics simulation model library, max2sim, for use with QuickSim II and QuickPath software.
./simlib/mentor/synlib | Contains the MAX+PLUS II synthesis library for use with AutoLogic II software, which supports synthesis for users running Mentor Graphics version B1.
./simlib/mentor/alt_mf | Contains the MAX+PLUS II macrofunction and megafunction libraries.
./simlib/mentor/alt_vtl | Contains the MAX+PLUS II VITAL library.

## Mentor Graphics/Exemplar Logic Design Entry Flow

The following figure shows the design entry flow for the MAX+PLUS® II/Mentor Graphics/Exemplar Logic interface.

#### Figure 1. MAX+PLUS II/Mentor Graphics/Exemplar Logic Design Entry Flow

| Alteraprovided items are shown in blue.

## Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software

You can create VHDL and Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project.

The MAX+PLUS II Text Editor offers the following advantages:

- Templates are available with the VHDL Templates and Verilog Templates commands (Template menu). These templates are also available in the ASCII vhdl.tmp and verilog.tmp files, respectively, which are located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can turn on the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL or Verilog HDL design file for use with the MAX+PLUS II software, go through the following steps:

1. Enter a VHDL or Verilog HDL design in the MAX+PLUS II Text Editor or another standard text editor and save it in your working directory.

2. Enter primitives, macrofunctions, and megafunctions in your VHDL or Verilog HDL design from the Altera library.

The following topics describe special steps needed to instantiate LPM and `clklock` functions:

- Instantiating LPM Functions in VHDL
- Instantiating the clklock Megafunction in VHDL or Verilog HDL

| You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software and Performing a Functional Simulation with QuickHDL Pro Software.

4. Once you have created a VHDL or Verilog HDL design, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:

- You can synthesize and optimize your design and create an EDIF netlist file, as described in Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software or Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software.

- You can use the Altera VHDL Express utility, vhd_exprss, to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and prepare the EDIF Output File for simulation with QuickHDL software, as described in Using the Altera Schematic Express (vhd_exprss) Utility.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL design files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software

After you have created a VHDL or Verilog HDL design, you can use Exemplar Logic's Leonardo software to synthesize and optimize your VHDL Design File (.vhd) or Verilog Design File (.v) and prepare it for compilation with the MAX+PLUS® II Compiler.

To synthesize and optimize your project and generate an EDIF netlist file with Leonardo software, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software.

4. Select the icon for your project's design file from the Navigator window, press Button 3, and choose max2_leonardo to start the Leonardo software and open the Exemplar Logic Leonardo window. You can also start Leonardo by typing `max2_leonardo` at the UNIX prompt.

5. Click Button 1 on the Flow Guide toolbar button to open the Customize Flow Guide dialog box.

6. Turn on the Altera EDIF Output File checkbox under Output Flow.

7. Choose Run Flow Guide to open the Flow Guide window and specify the appropriate options in the following modules to synthesize your project:

1. Choose Load Library to open the Load Library dialog box. If necessary, select FPGA Enhanced from the Tech Type drop-down list box. Select the target Altera® device family from the list of supported device families and choose Load to close the dialog box.

2. Choose Read to open the Read dialog box. Turn on VHDL or Verilog HDL under Format, ensure that the appropriate library name appears under Work Library, and type the name of your design file in the Filename box or select it from the Select a File dialog box. Choose Read to close the dialog box.

3. Choose Pre-Optimize to open the Pre-Optimize dialog box. Choose Pre-Optimize to accept the default pre-optimization settings and close the dialog box.

4. Choose Optimize to open the Optimize dialog box. Choose Optimize to accept the default optimization settings and close the dialog box.

5. Choose Write Altera to open the Convenience Procedures dialog box. Type `write_altera` in the Procedure box or select write_altera from the list box and choose Run to automatically generate <design name>.edf.

8. Choose Exit Flow Guide to return to the Leonardo window.

9. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL Design Files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

| Refer to the following sources for additional information:

- Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

- Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   | Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   | You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type `setacf -h` and `maxplus2 -h` for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      | If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than `VCC` or `GND` for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   - Exemplar Logic Galileo Extreme-Specific Compiler Settings
   - Synopsys DesignWare-Specific Compiler Settings
   - Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   - Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      | This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   | See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

- JEDEC Files (.jed)
- Programmer Object Files (.pof)
- SRAM Object Files (.sof)
- Hexadecimal (Intel-format) Files (.hex)
- Tabular Text Files (.ttf)

| Refer to the following sources for additional information:

- Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
- Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
- Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware

## Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS® II software, you can program an Altera® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

#### Figure 1. MAX+PLUS II Device Programming Flow

| Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

##### Table 1. Altera Programming Hardware

Programming Hardware Option | PCs | UNIX Work- stations | ACEX® 1K Devices | MAX® 3000A Devices | Classic® & MAX 5000 Devices | MAX 7000 & MAX 7000E Devices | MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000
&
MAX 9000A
Devices

FLEX® 6000,
FLEX 6000A,
FLEX 8000,
FLEX 10K,
FLEX 10KA,
FLEX 10KB,
&
FLEX 10KE Devices
In-System
Programming/
Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and
device-specific
adapters
BitBlaster™ Download Cable |  |  |  |  |  |  |  |  |
ByteBlasterMV™ Download Cable |  |  |  |  |  |  |  |  |
MasterBlaster™ Download Cable |  |  |  |  |  |  |  |  |

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

| Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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