## Using Synopsys FPGA Express & MAX+PLUS II Software

The following topics describe how to use the FPGA Express and MAX+PLUS® II software. Click on one of the following topics for more information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Software Requirements

### Design Flow for FPGA Express Software

### Design Entry

- #### Design Entry Flow

- #### VHDL

  - Creating VHDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
    - Instantiating LPM Functions in VHDL
    - Instantiating RAM & ROM Functions in VHDL

- #### Verilog HDL

  - Creating Verilog HDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
    - Instantiating LPM Functions in Verilog HDL
    - Instantiating RAM & ROM Functions in Verilog HDL

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software
- Entering Resource, Device & Global Logic Synthesis Assignments
  - Assigning a Device & Clock Frequency (fMAX)
  - Assigning Pins, Logic Options, and tSU, tCO and tPD Timing Constraints
  - Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express Software
  - Using ACFs Generated by FPGA Express Software
  - Modifying the Assignment & Configuration File with the setacf Utility
- Analyzing Estimated Timing with the FPGA Express Time Tracker
- Specifying Speed/Area & CPU Effort Settings with the FPGA Express Software

### Compilation

- Project Compilation Flow
- Compiling Projects with MAX+PLUS II Software

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Programming Altera Devices
- Using Synopsys Design Compiler or FPGA Compiler & MAX+PLUS II Software
- Using Synopsys PrimeTime & MAX+PLUS II Software
- Using Synopsys VSS & MAX+PLUS II Software

| Go to the following topics, which are available on the web, for additional information:

- About the MAX+PLUS II Software
- Altera Programming Hardware
- Synopsys web site (http://www.synopsys.com)

## MAX+PLUS II/FPGA Express Software Requirements

Table 1 shows the software applications that are used to generate, process, synthesize, and verify a project with MAX+PLUS® II and FPGA Express software:

Table 1. Software Requirements
Synopsys | Altera
FPGA Express version 2.1 | MAX+PLUS II version 9.2 and higher

The FPGA Express software supports devices from all FLEX device families and the MAX 7000 and MAX 9000 device families.

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Synopsys applications are supported by the current version of the MAX+PLUS II software. It also provides information on installation and operating requirements. You should read the read.me file on the MAX+PLUS II CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

| Go to the FPGA Express release notes for information on installing the FPGA Express software and a description of its latest changes. These notes are available in the readme.htm file on the FPGA Express installation CD-ROM.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX 7000 Devices
- MAX 9000 Devices

## Design Flow for FPGA Express Software

Figure 1 shows the design flow for the MAX+PLUS® II/FPGA Express interface.

Figure 1. MAX+PLUS II/FPGA Express Design Flow

## FPGA Express Design Entry Flow

Figure 1 shows the design entry flow for the MAX+PLUS® II/FPGA Express interface.

Figure 1. MAX+PLUS II/FPGA Express Design Entry Flow

| Altera-provided items are shown in blue.

## Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS® II Text Editor, the FPGA Express internal text editor, or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II and FPGA Express text editors offer different advantages; use either or both depending on your personal preferences:

- The MAX+PLUS II Text Editor offers VHDL templates with the VHDL Templates command (Templates menu) and syntax coloring with the Syntax Coloring command (Options menu).

- The FPGA Express internal text editor provides automatic error location when you double-click an error in the Output window.

To create a VHDL design that can be synthesized and optimized with the FPGA Express software, follow these steps:

1. Describe your design using FPGA Express-supported VHDL constructs. For information on synthesizable VHDL constructs, refer to the online VHDL Reference Manual provided with the FPGA Express software. The following topics describe how to instantiate additional Altera-specific logic functions in your design:
   - Instantiating the clklock Megafunction in VHDL or Verilog HDL
   - Instantiating RAM & ROM Functions in VHDL
   - Instantiating LPM Functions in VHDL

   | You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. Once you have created a design, synthesize and optimize it, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Using Synopsys VSS & MAX+PLUS II Software
- Compiling Projects with MAX+PLUS II Software

| Go to the following topics, which are available on the web, for additional information:

- Altera Megafunction Partners Program (AMPP)
- Altera Megafunctions

## Instantiating the clklock Megafunction in VHDL or Verilog HDL

MAX+PLUS® II interfaces to other EDA tools support the `clklock` phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility, which is available in the MAX+PLUS II system directory. Type `gencklk -h` at the DOS or UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).

The gencklk utility allows parameters for the `clklock` function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the `clklock` function name; therefore, the values do not need to be declared explicitly.

To instantiate the `clklock` megafunction in VHDL or Verilog HDL, go through the following steps:

1. Type the following command at the DOS or UNIX prompt to generate the `clklock_`x`_`y function, where x is the ClockBoost™ value and y is the input frequency in MHz:

   | Type `gencklk` <ClockBoost> <input frequency>`-vhdl` for VHDL designs.

   or:

   | Type `gencklk` <ClockBoost> <input frequency> `-verilog` for Verilog HDL designs.

   Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the `clklock` megafunction.

2. Create a design file that instantiates the `clklock``_`x`_`y.vhd or `clklock`_x_y.v file. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.

| In MAX+PLUS II version 8.3 and lower, running `genclklk` on a PC always creates files named as clklock.vhd, clklock.cmp, and clklock.v, regardless of the ClockBoost and input frequency values you specify.

Figures 1 and 2 show a `clklock` function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.

Figure 1. VHDL Design File with clklock Instantiation (count8.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY altera;
    USE altera.maxplus2.all;     --  Include Altera Component Declarations
    ENTITY count8 IS
       PORT (a    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             ldn  : IN STD_LOGIC;
             gn   : IN STD_LOGIC;
             dnup : IN STD_LOGIC;
             setn : IN STD_LOGIC;
             clrn : IN STD_LOGIC;
             clk  : IN STD_LOGIC;
             co   : OUT STD_LOGIC;
             q    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END count8;
    ARCHITECTURE structure OF count8 IS
       signal clk2x : STD_LOGIC;
    COMPONENT clklock_2_40
       PORT (
          INCLK : IN STD_LOGIC;
          OUTCLK : OUT STD_LOGIC
       );
    END COMPONENT;
    BEGIN
       u1: clklock_2_40
       PORT MAP (inclk=>clk, outclk=>clk2x);
       u2: a_8count
       PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
                 e=>a(4), f=>a(5), g=>a(6), h=>a(7),
                 clk=>clk2x,
                 ldn=>ldn,
                 gn=>gn,
                 dnup=>dnup,
                 setn=>setn,
                 clrn=>clrn,
                 qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
                 qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
                 cout=>co);
     END structure;

Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v)
    `timescale 1ns / 10ps
    module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q);
    output          co;
    output[7:0]     q;
    input[7:0]      a;
    input           ldn, gn,dnup, setn, clrn, clk;
    wire            clk2x;
    clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) );
    A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]),
                 .G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
                 .SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
                 .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
                 .QH(q[7]), .COUT(co) );
    endmodule

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating LPM Functions in VHDL

You can enter library of parameterized modules (LPM) functions in your VHDL design. The MAX+PLUS® II software supports all LPM functions except the truth table, finite state machine, and pad functions. The FPGA Express software supports all LPM functions that are supported in the MAX+PLUS II software except the `lpm_and`, `lpm_or`, `lpm_xor`, and `lpm_mux` functions. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on all LPM functions.

To instantiate an LPM function in a VHDL design, follow these steps:

1. Create an instance of an LPM function in VHDL with a Component Instantiation Statement. VHDL Component Declarations for LPM functions are available in MAX+PLUS II Help and also installed automatically in the following FPGA Express directory:

   <drive>:\synopsys\fpga_express\lib\packages\lpm\lpm_components.vhd

   Use named association to specify parameter values in the Generic Map Clauses of LPM function instantiations. Figure 1 shows the Component Declaration for the `lpm_ram_dq` function.

   Figure 1. Component Declaration for lpm_ram_dq (from lpm_components.vhd)

       COMPONENT lpm_ram_dq
          GENERIC (
                   LPM_WIDTH: POSITIVE;
                   LPM_TYPE : STRING := L_RAM_DQ;
                   LPM_WIDTHAD: POSITIVE;
                   LPM_NUMWORDS: STRING := UNUSED;
                   LPM_FILE: STRING := UNUSED;
                   LPM_INDATA: STRING := REGISTERED;
                   LPM_ADDRESS_CONTROL : STRING := REGISTERED;
                   LPM_OUTDATA: STRING := REGISTERED
                   );
          PORT    (
                   data     : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
                   we       : IN STD_LOGIC := '1';
                   inclock  : IN STD_LOGIC := '1';
                   outclock : IN STD_LOGIC := '1';
                   address  : IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
                   q        : OUT STD_LOGIC_VECTOR (LPM_WIDTH-1 DOWNTO 0)
                  );
       END COMPONENT;

2. Manually tie any pins that require an initial value of logic 1 to `vcc`. The FPGA Express software does not support initial values of logic 1 in Component Declarations. However, it does support initial values of logic 0.

   Figure 2 shows an example of instantiating an `lpm_ram_dq` function in VHDL.

   Figure 2. VHDL Design File with lpm_ram_dq Instantiation

       LIBRARY ieee;
       USE ieee.std_logic_1164.all;
       LIBRARY lpm;
       USE lpm.lpm_components.all;

       ENTITY design IS
          PORT(
               din  : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
               we   : IN STD_LOGIC;
               clk  : IN STD_LOGIC;
               addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
               dat  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
               );
       END design;

       ARCHITECTURE struct OF design IS
          SIGNAL vcc : STD_LOGIC;

       BEGIN  --  struct
          vcc <= '1';

       u1:  lpm_ram_dq
          GENERIC MAP(
                      LPM_WIDTH   => 16,
                      LPM_WIDTHAD => 4,
                      LPM_INDATA  => "UNREGISTERED",
                      LPM_OUTDATA => "UNREGISTERED"
                     )

          PORT MAP(
                   data     => din,
                   address  => addr,
                   we       => we,
                   q        => dat,
                   inclock  => vcc,
                   outclock => clk
                   );
       END struct;

3. Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.

## Instantiating RAM & ROM Functions in VHDL

The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX®10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. Altera recommends using the LPM functions `lpm_ram_dq`, `lpm_ram_io`, and `lpm_rom` to instantiate synchronous and asynchronous RAM and ROM. However, if you wish to enter cycle-shared dual port RAM (`csdpram`), dual-port RAM (`altdpram`), single-Clock FIFO (`scfifo`), and dual-clock FIFO (`dcfifo`) functions, or if you wish to create simulation models for any supported RAM or ROM function, you can use the Altera-provided genmem utility. Instantiations created with genmem for use with other Synopsys products, such as FPGA Compiler or Design Compiler, are supported for backward compatibility. Type `genmem` at the DOS or UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.

To instantiate an `lpm_ram_dq`, `lpm_ram_io`, or `lpm_rom` function:

| Follow the guidelines in Instantiating LPM Functions in VHDL.

To instantiate other RAM and ROM functions in VHDL, follow these steps:

1. Use the genmem utility to generate a memory model by typing the following command at the DOS or UNIX prompt:

   `genmem` <memory type>`` <memory size>`-vhdl`

   For example: `genmem scfifo 16x8 -vhdl`

2. Create a VHDL design that incorporates the text from the genmem-generated Component Declaration, <memory name>.cmp, and instantiate the <memory name>.vhd function. The genmem utility produces files with descriptive names that typically include both the memory type and the memory size (e.g., scfifo_16x8_d.vhd).

| In MAX+PLUS II version 8.3 and lower, running `genmem` on a PC always creates files named as genmem.vhd, genmem.cmp, and genmem.v, regardless of the memory type and memory size you specify.

3. (Optional for RAM functions) Specify an initial memory content file:

   - For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Generic Map Clause, with the `LPM_FILE` parameter. The filename must be the same as the instance name; e.g., the `u1` instance name shown in Figure 1 must be unique throughout the whole project, and must contain only valid VHDL name characters. The initialization file must reside in the directory containing the project's design files.

   - For RAM functions, specifying memory initialization file is optional. If you want to use it, you must specify it in the Generic Map Clause as described above. If you do not use an initialization file, you should not declare or use the Generic Clause.

     1. The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use an MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.

     2. If you use an Intel hexadecimal format file and wish to simulate the file with the VHDL System Simulator (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.

4. Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.

| Go to Using Synopsys VSS & MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS® II Text Editor, the FPGA Express internal text editor, or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II and FPGA Express text editors offer different advantages; use either or both depending on your personal preferences:

- The MAX+PLUS II Text Editor offers Verilog HDL templates with the Verilog HDL Templates command (Templates menu) and syntax coloring with the Syntax Coloring command (Options menu).

- The FPGA Express internal text editor provides automatic error location when you double-click an error in the Output window.

To create a Verilog HDL design that can be synthesized and optimized with the FPGA Express software, follow these steps:

1. Describe your design using FPGA Express-supported Verilog HDL constructs. For information on synthesizable Verilog HDL constructs, refer to the online HDL Reference Manual provided with the FPGA Express software. The following topics describe how to instantiate additional Altera-specific logic functions in your design:
   - Instantiating the clklock Megafunction in VHDL or Verilog HDL
   - Instantiating RAM & ROM Functions in Verilog HDL
   - Instantiating LPM Functions in Verilog HDL

   | You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. Once you have created a design, synthesize and optimize it, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- Altera Megafunction Partners Program (AMPP)
- Altera Megafunctions

## Instantiating LPM Functions in Verilog HDL

You can enter library of parameterized modules (LPM) functions in your Verilog HDL design. The MAX+PLUS® II software supports all LPM functions except the truth table, finite state machine, and pad functions. The FPGA Express software supports all LPM functions that are supported in the MAX+PLUS II software except the `lpm_and`, `lpm_or`, `lpm_xor`, and `lpm_mux` functions. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on all LPM functions.

To instantiate an LPM function in a Verilog HDL design, follow these steps:

1. Use a Module Instantiation to instantiate an LPM function. You must associate all parameters, and only positional association is allowed.

   Figure 1 shows an example of instantiating an `lpm_ram_dq` function in Verilog HDL.

   Figure 1. Verilog HDL Design File with lpm_ram_dq Instantiation

       // RAM design

       module design(din, we, clk, addr, dat);

       input [15:0] din;
       input we, clk;
       input [3:0] addr;
       output [15:0] dat;

       supply1 vcc;

       lpm_ram_dq #(
       16,			// LPM_WIDTH
       "LPM_RAM_DQ",		// LPM_TYPE
       4,			// LPM_WIDTHAD
       16,			// LPM_NUMWORDS
       "UNUSED",		// LPM_FILE
       "UNREGISTERED",		// LPM_INDATA
       "UNREGISTERED", 	// LPM_ADDRESS_CONTROL
       "UNREGISTERED" 		// LPM_OUTDATA
       )

       u1(
       .data(din),
       .address(addr),
       .we(we),
       .q(dat),
       .inclock(vcc),
       .outclock(clk)
       );

       endmodule

2. Continue with the steps necessary to complete your Verilog HDL design file, as described in Creating Verilog HDL Designs for Use with MAX+PLUS II Software.

## Instantiating RAM & ROM Functions in Verilog HDL

The MAX+PLUS® II/Synopsys interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual port RAM, dual-port RAM, single-Clock FIFO, and dual-clock FIFO functions. Altera recommends using the LPM functions `lpm_ram_dq`, `lpm_ram_io`, and `lpm_rom` to instantiate synchronous and asynchronous RAM and ROM. However, if you wish to enter cycle-shared dual port ram (`csdpram`), dual-port RAM (`altdpram`), single-Clock FIFO (`scfifo`), and dual-clock FIFO (`dcfifo`) functions, or if you wish create simulation models for any supported RAM or ROM function, you can use the Altera-provided genmem utility. Designs that instantiate genmem-generated synchronous and asynchronous RAM and ROM -- such as those used with FPGA Compiler or Design Compiler -- are supported for backward compatibility. Type `genmem` at the DOS or UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.

To instantiate an `lpm_ram_dq`, `lpm_ram_io`, or `lpm_rom` function:

| Follow the guidelines in Instantiating LPM Functions in Verilog HDL.

To instantiate other RAM and ROM functions in Verilog HDL, follow these steps:

1. Use the genmem utility to generate a memory model by typing the following command at a DOS or UNIX prompt:

   `genmem` <memory type>`` <memory size>`-verilog`

   For example: `genmem scfifo 16x8 -verilog`

2. Create a Verilog HDL design that instantiates the <memory name>.v function. The genmem utility produces files with descriptive names that typically include both the memory type and the memory size (e.g., scfifo_16x8_d.v).

   | In MAX+PLUS II version 8.3 and lower, running `genmem` on a PC always creates files named as genmem.vhd, genmem.cmp, and genmem.v, regardless of the memory type and memory size values you specify.

3. (Optional for RAM functions) Specify an initial memory content file:

   - For ROM functions, you must specify the filename of an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format in the Parameter Statement, using the `LPM_FILE` parameter. The filename must be the same as the instance name; e.g., the `u1` instance name must be unique throughout the whole project, and must contain only valid Verilog HDL name characters. The initialization file must reside in the directory containing the project's design files.

   - For RAM functions, specifying a memory initialization file is optional. If you want to use it, you must specify it in the Parameter Statement as described above.

1. The MIF format is supported only for specifying initial memory content when compiling designs within MAX+PLUS II software. You cannot use an MIF to perform simulation with Synopsys tools prior to MAX+PLUS II compilation.

2. If you use an Intel hexadecimal format file and wish to simulate the file with the VHDL System Simulator Software (VSS) after MAX+PLUS II compilation, you should use the Synopsys intelhex utility to translate the Intel hexadecimal fomat file into a VSS-compatible Synopsys memory file. Refer to the Synopsys VHDL System Simulator Software Tool manual for details about using the intelhex utility.

4. Continue with the steps necessary to complete your Verilog HDL design, as described in Creating Verilog HDL Designs for Use with MAX+PLUS II Software.

| Go to FLEX 10K Devices, which is available on the web, for additional information.

## Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software

You can analyze, synthesize, and optimize design files using the FPGA Express software, then convert them to EDIF netlist files that can be processed by the MAX+PLUS® II software.

To process a VHDL or Verilog HDL design for use with MAX+PLUS II software, follow these steps:

1. Create a VHDL file, <design name>.vhd, or Verilog HDL file, <design name>.v, using the MAX+PLUS II Text Editor or another standard text editor and save it in your working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software or Creating Verilog HDL Designs for Use with MAX+PLUS II Software for more information on VHDL or Verilog HDL design entry.

2. Start the FPGA Express software. Select Create a new project in the Startup dialog box and choose OK. The Create Project Folder dialog box is displayed. You can also view the Create Project Folder dialog box by choosing New (File menu).

3. Specify the full file and path name of the project in the Create Project Folder dialog box and choose Create. The FPGA Express software creates the project and opens the Identify Source File dialog box.

4. Identify and analyze the source files for the project by selecting them in the Identify Source File dialog box and choosing Add. The FPGA Express internal text editor automatically analyzes each source file as it appears on the left-hand side of the Project window. A green checkmark appears to the left of each filename for the files that have no errors or warnings; a red cross appears for files with errors; and an exclamation point appears for files with warnings.

5. Select the source file icon to display any errors or warnings in the Output window. To fix an error, double-click on the error. The FPGA Express internal text editor automatically displays the source file and highlights the line containing the error or warning in red. To view help on the error or warning, double-click on the error or warning code number (shown in parentheses) in the Output window.

   | FPGA Express software does not copy source files; it identifies and analyzes them in their current location. Refer to FPGA Express Help for more information.

6. Specify the MAX+PLUS II logic synthesis style. Refer to Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express software for more information.

7. From the Project window, identify the top-level design for your project. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.

8. In the Create Implementation dialog box, specify the following options:

   1. Assign a device and the Clock frequency. Refer to Assigning a Device & Clock Frequency (fMAX) for more information.

   2. Select a global optimization goal (speed or area) and a CPU effort designation (high or low). Refer to Specifying the Speed/Area & CPU Effort Settings with the FPGA Express Software for information.

   3. Close the Create Implementation dialog box by choosing OK.

   The FPGA Express software processes each source file and determines the complete hierarchical structure and topology of the design, including multi-level links and references between subdesigns. With this information, the FPGA Express software produces an intermediate, unoptimized design implementation. The right-hand side of the Project window displays the implementation name and target device. The implementation icon also indicates any errors, warnings, or other information. To correct error or warning conditions, refer to step 5.

9. (Optional) Select the design implementation icon in the Chips window, press Button 2, and choose the Edit Constraints command from the pop-up menu to display the Altera-specific constraint tables. These constraint tables allow you to specify pin, logic option, and timing assignments for your design. All design-specific information, such as Clock names, port names, and design hierarchy assignments is extracted automatically from the design. Altera recommends entering specific requirements directly into these tables to obtain the desired optimization. Refer to Entering Resource, Device & Global Logic Synthesis Assignments for information.

10. Optimize the design by selecting the design implementation in the Project window and choosing the Optimize button on the toolbar. A new optimized implementation icon appears beneath the original implementation icon. When you open the optimized implementation, the constraint tables are back-annotated with the optimization results. The FPGA Express software optimizes a design for either speed or area, based on the settings you specified in step 8.

11. Identify and optimize critical paths in your design with the Time Tracker static timing analyzer, as described in Analyzing Estimated Timing with the FPGA Express Time Tracker.

12. Generate a project report by selecting the optimized design implementation and clicking the Report icon on the toolbar. An FPGA Express project report documents the design through the synthesis and optimization design flow. The report includes information about design source data, constraints, and optimization options.

13. Generate MAX+PLUS II-compatible EDIF netlist files by selecting the optimized design implementation and choosing the Export Netlist button on the toolbar. In the Export dialog box, specify the following options:

    1. Specify the name and location of the directory for the EDIF netlist files in the Export Directory box.

    2. Select the EDIF netlist file's output bus from the Bus Style drop-down list. The MAX+PLUS II software accepts either flattened or unflattened buses. In the FPGA Express software, the default setting, EXPAND, flattens each bus by writing each bus bit as an individual I/O port. To export an EDIF netlist file without flattening the bus names, select any of the other settings, which include delimiters for different bus notations:`[]`, `<>`, `()`, and `{}`.

    3. If you wish to generate a VHDL or Verilog HDL netlist file for functional simulation prior to MAX+PLUS II compilation, select a language option (VHDL or Verilog) from the Output Format drop-down list. Otherwise, select NONE for this option instead.

    4. Turn on the Export Primitives option to export VHDL or Verilog HDL primitives into the simulation netlist file. However, if the simulation is to be performed with an external library, turn the option off.

    5. Close the Export dialog box by choosing OK. The FPGA Express software creates the following MAX+PLUS II-compatible files:

       - <design name>.edf (EDIF format)
       - <design name>.acf, an Assignment & Configuration File that contains design constraints
       - <design name>.lmf, a Library Mapping File that maps FPGA Express functions to MAX+PLUS II functions

14. Copy all three types of output files (EDIF netlist file(s), ACF, and LMF) to a MAX+PLUS II project directory. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

## Entering Resource, Device & Global Logic Synthesis Assignments

The MAX+PLUS® II software allows you to enter a variety of resource, device, and global logic synthesis assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. With MAX+PLUS II software, you can enter all types of resource, device, and global logic synthesis assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project.

In the Synopsys FPGA Express software, you can assign a limited subset of these assignments in the Create Implementation dialog box, in the Options dialog box, and by specifying options in constraint tables. These attributes are incorporated into the ACF generated by the FPGA Express software. Refer to the following topics for more information:

- Assigning a Device & Clock Frequency (fMAX)
- Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints
- Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express Software
- Using ACFs Generated by FPGA Express Software
- Modifying the Assignment & Configuration File with the setacf utility

| Go to the following sources for related information:

- FPGA Express Help
- "resource assignments" or "ACF, format" in MAX+PLUS II Help
- Specifying the Speed/Area & CPU Effort Settings with the FPGA Express Software in these MAX+PLUS II ACCESSSM Key topics

## Assigning a Device & Clock Frequency (fMAX)

You can specify the desired Clock frequency (called fMAX in the MAX+PLUS® II software) and the target device family before synthesizing and optimizing the design with the FPGA Express software. You can optionally select a specific device and speed grade within the target device family. These assignments are stored in the design's Assignment & Configuration File, <design name>.acf, which is generated automatically by the FPGA Express software.

To assign a device or device family and the Clock frequency, follow these steps:

1. If you have not already done so, identify the top-level design for your project from the Design Sources window. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.

2. Enter an implementation name in the Implementation Name box. If you do not enter a name, FPGA Express software automatically creates a unique implementation name.

3. Select Altera from the Vendor list.

4. Select the appropriate Altera device family from the Family list.

5. (Optional) Select a specific device from the Device list, and select a specific speed grade from the Speed Grade list.

6. Type the desired Clock frequency in the Clock Frequency text box. This Clock frequency is used as the default value for all Clock signals in the design.

7. (Optional) Select speed/area and CPU effort settings, as described in Specifying the Speed/Area & CPU Effort Settings with the FPGA Express Software.

8. Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

| You can also edit the Clock frequency by double-clicking on the design implementation name to open the constraint tables and entering information on the Clock tab. For more information, refer to Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints.

| Go to the following sources for related information:

- FPGA Express Help
- "Guidelines for Achieving Maximum Speed Performance" in MAX+PLUS II Help

## Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints

You can assign pins, logic options, or timing constraints to your design in FPGA Express constraint tables. Some design-specific information is extracted automatically from your design and displayed in the constraint tables; you can also manually enter specific assignments in these tables. The FPGA Express software saves the assignments to an Assignment & Configuration File (.acf) when it synthesizes and optimizes the design. The MAX+PLUS® II software uses the assignment information from the ACF when it processes the design. Refer to Using ACFs Generated by FPGA Express Software for more information.

To enter resource assignments in FPGA Express software, follow these steps:

1. Select the design implementation icon in the Chips window, press Button 2, and choose the Edit Constraints commmand from the pop-up menu to display the Altera-specific constraint tables. These tables allow you to specify resource assignments for your design. All design-specific information such as Clock names, port names, and design hierarchy is extracted automatically from the design. Altera recommends entering specific requirements directly into these tables to obtain the desired optimization. For information on creating a design implementation, refer to steps 1 through 8 in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

2. Enter assignments in the appropriate constraint tables. You can click on a tab to toggle between tables. Refer to Table 1, which shows the available MAX+PLUS II resource assignment options in the FPGA Express constraint tables. The Clock and Path tables already contain information that you previously entered in the Create Implementation dialog box. Refer to Assigning a Device & Clock Frequency (fMAX) for more information.

   Table 1. MAX+PLUS II Resource Assignments in FPGA Express Constraint Tables

   MAX+PLUS II Resource Assignment | Equivalent FPGA Express Constraint Table Setting
   Tab Name | Action
   Pin assignment | Ports | Specify the pin number in the Pad Location column.
   tSU timing assignment | Ports | Specify the time in the Input Delay column.
   tCO timing assignment | Ports | Specify the time in the Output Delay column.
   Slow Slew Rate logic option assignment | Ports | Click on the appropriate cell in the Slew Rate column and select <default>, FAST, or SLOW from the list.
   Fast I/O logic option assignment | Ports | Click on the appropriate cell in the Use I/O Reg column and select <default>, ON, or OFF from the list.
   tPD timing assignment | Paths | Specify the time in the Delay column.

3. Choose Save and then Close to exit from the FPGA Express constraint tables.

| Go to the following sources for related information:

- FPGA Express Help
- "Guidelines for Achieving Maximum Speed Performance" in MAX+PLUS II Help
- Specifying the MAX+PLUS II Logic Synthesis Style with the FPGA Express Software in these MAX+PLUS II ACCESSSM Key topics

## Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express Software

You can specify the MAX+PLUS® II global project logic synthesis style for FLEX® devices from within the FPGA Express software. To specify the global project logic synthesis style, follow these steps:

1. Choose Options (Synthesis menu) to display the Options dialog box.
2. Choose the Behavior tab.
3. Turn the Insert LCELL Buffers, Style WYSIWYG (Altera FLEX Only) option on or off:

   - Turning this option on is the equivalent of specifying the WYSIWYG (What You See Is What You Get) logic synthesis style in the MAX+PLUS II software. The WYSIWYG style directs the Compiler's Logic Synthesizer module to change the logic in your project as little as possible during compilation. The WYSIWYG style avoids removing or inserting additional logic, and turns off many logic options that might help the project to fit. In addition, if this option is turned on, the FPGA Express software inserts `LCELL` buffers for look-up table (LUT) outputs so that the MAX+PLUS II software will not alter the logic cell implementations. This option is recommended when a design's area optimization has priority over its speed.

   - Turning this option off is the equivalent of specifying the Fast logic synthesis style in the MAX+PLUS II software. The Fast style directs the Compiler's Logic Synthesizer module to optimize your project for maximum speed, rather than for minimum silicon usage. In addition, if this option is turned off, the FPGA Express software does not insert `LCELL` buffers, thereby allowing the MAX+PLUS II software to optimize the LUT logic to improve performance.
4. Choose OK.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX® Devices
- Classic Device Family

## Using ACFs Generated by FPGA Express Software

With FPGA Express software, you can either generate a new Assignment & Configuration File (.acf), along with an EDIF netlist file (.edf) and Library Mapping File (.lmf), to be imported into the MAX+PLUS® II software, or you can place a copy of an existing ACF in the FPGA Express output directory. If you use an existing ACF, FPGA Express updates the ACF with additional information, such as the global project synthesis style, as it processes the design. Each line in the ACF that is modified by the FPGA Express software is marked with a `{synopsys}` comment at the end. You should then place this ACF in the MAX+PLUS II project directory.

| If an existing ACF has been modified by FPGA Express, then processed by the MAX+PLUS II Compiler, the resulting ACF may specify an incorrect LMF. If so, the MAX+PLUS II software displays the error message `Can't find design file` <cell name>. You can correct this error in MAX+PLUS II software by specifying the FPGA Express-generated <project name>.lmf file in the LMF #1 box in the EDIF Netlist Reader Settings dialog box. See Compiling Projects with MAX+PLUS II Software for more information.

The ACF incorporates the following assignments from FPGA Express software and passes them to the MAX+PLUS II software:

- The Altera device family and optional specific device and speed grade specified in the Create Implementation dialog box
- The global project logic synthesis style specified in the Create Implementation dialog box
- The Clock frequency (fMAX) specified in the Create Implementation dialog box or the Clocks constraint table
- Clock speeds (tPD) specified in the Clocks constraint table
- Path group constraints specified in the Paths constraint table
- Pin assignments; settings for the Slow Slew Rate and Fast I/O logic options; and input-to-setup (tSU) and clock-to-output (tCO) delays specified in the Ports constraint table

Figure 1 shows an example of a typical ACF generated by the FPGA Express software.

Figure 1. FPGA Express-Generated Assignment & Configuration File

    CHIP my_chip
    	DEVICE = EPF10K100GC503-3 {synopsys};
    	"|_CONFIG" : PIN = P40 {synopsys};
    	"|_STATUS" : PIN = P41 {synopsys};

    GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
    	DEVICE_FAMILY = FLEX10K {synopsys};
    	STYLE = WYSIWYG {synopsys};
    	OPTIMIZE_FOR_SPEED = 5 {synopsys};
    	AUTO_GLOBAL_CLOCK = ON {synopsys};

    LOGIC_OPTIONS
    	"|TX_FIFOA_D6" : IO_CELL_REGISTER = ON {synopsys};
    	"|DEST_RAM_D6" : SLOW_SLEW_RATE = ON {synopsys};
    	"|DEST_RAM_D5" : SLOW_SLEW_RATE = OFF {synopsys};

    COMPILER_INTERFACES_CONFIGURATION
    	EDIF_INPUT_VCC = VDD {synopsys};
    	EDIF_INPUT_GND = GND {synopsys};
    	EDIF_INPUT_USE_LMF1 = ON {synopsys};
    	EDIF_INPUT_LMF1 = "my_chip.lmf" {synopsys};

    TIMING_POINT
    	FREQUENCY = 50MHz {synopsys};
    	"CLK80" : FREQUENCY = 80MHz {synopsys};
    	"G" : FREQUENCY = 25MHz {synopsys};
    	TPD = 10ns {synopsys};
    	"inp1" : TSU = 20ns {synopsys};
    	"out1" : TCO = 15ns {synopsys};

| FPGA Express-generated ACFs show the Fast I/O logic option as `IO_CELL_REGISTER`. The MAX+PLUS II software automatically interprets this assignment as a `FAST_IO` assignment.

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## Analyzing Estimated Timing with the FPGA Express Time Tracker

You can use the FPGA Express Time Tracker static timing analyzer to display estimated delays of critical paths in your project. This timing analyzer provides timing information and a detailed listing of critical paths.

To use the Time Tracker timing analyzer, follow these steps:

1. Select the design implementation icon in the Chips window, press Button 2, and choose the View Results commmand from the pop-up menu to display the Time Tracker tabs.

2. Analyze the timing of your design by viewing the different tables within the Clocks, Paths, and Ports Time Tracker tabs:

   - To analyze the Clock frequency (fMAX), select the Clocks tab. The table on the Clocks tab contains a column showing the actual Clock frequency for each Clock in your design next to the desired frequency derived from your timing constraints. Clocks that fail to meet their constraints are highlighted in red.

   - To check critical timing paths, select the Paths tab. The table on the Paths tab contains an Est. Delay column displaying path delays. Paths that fail to meet constraints are highlighted in red. You can select a path or path group to display additional tables with increasing detail, in order to identify exactly which paths failed to meet their timing constraints.
   - To view I/O port delays, select the Ports tab. The Ports tab displays the slack for each I/O port, i.e., the Clock period minus the propagation delay through the port in the Input Slack column for input ports and the Output Slack column for output ports. Negative values are highlighted in red, indicating that the propagation delay exceeds the Clock period, causing a timing violation.

3. If necessary, change the design logic or adjust your timing constraints as described in Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints, then re-optimize the design.

4. Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

## Specifying Speed/Area & CPU Effort Settings with the FPGA Express Software

FPGA Express software allows you to choose either speed or area options and to specify either high or low CPU effort in logic optimization. Optimization goals are set on a global basis or on particular levels of hierarchy.

To set global optimization controls in the FPGA Express software, follow these steps:

1. If you have not already done so, identify the top-level design for your project in the Design Sources window. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.

2. Select either speed or area under Optimize for to specify the optimization goal for the entire design:

   - Selecting the speed option minimizes delay by synthesizing circuits to contain the least number of levels of combinatorial logic, sometimes yielding increased design area. This setting maximizes operating frequency and minimizes combinatorial path delays.

   - Selecting the area option minimizes the combinatorial logic resources used, sometimes yielding reduced speed. This setting minimizes combinatorial logic usage. Altera also recommends selecting the WYSIWYG synthesis style when optimizing for area, as described in Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express Software.

3. Select either high or low under Effort to specify the CPU effort level:

   - Selecting the low option increases compilation speed at the expense of larger combinatorial area. This option is most useful for minimizing compilation time for very large designs when neither speed nor area are critical.

   - Selecting the high option decreases the combinatorial area at the expense of compilation speed. This option is recommended in speed- or area-critical designs.

You can set the same optimization controls on individual levels of hierarchy for greater control. This strategy is useful when your design contains hierarchical blocks with different requirements. For example, some blocks may be time-critical while others are not. To obtain the best resuls, you should optimize time-critical blocks for speed and other blocks for area.

To set optimization goals on a particular level of hierarchy, follow these steps:

1. Select the pre-optimized chip icon in the Chips window, press Button 2 and choose Edit Constraints to display the constraints tables.
2. Select the Modules tab.
3. Find the row that displays the level of hierarchy for which you want to set an optimization goal.
4. In the Optimize for column of that row, click inside the cell and select either speed or area from the options that appear.
5. In the Effort column of that row, click inside the cell and select either high or low from the available options.

6. If you have not already done so, assign a device and Clock frequency, as described in Assigning a Device & Clock Frequency (fMAX).

7. Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

| Optimization settings are the same for an entire design file, regardless of its level of hierarchy.

## MAX+PLUS II/FPGA Express Project Compilation Flow

Figure 1 below shows the project compilation flow for the MAX+PLUS® II/FPGA Express interface.

Figure 1. MAX+PLUS II/FPGA Express Project Compilation Flow

| Altera-provided items are shown in blue.

## Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

| Refer to the following sources for additional information:

- Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

- Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   | Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   | You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type `setacf -h` and `maxplus2 -h` for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      | If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than `VCC` or `GND` for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   - Exemplar Logic Galileo Extreme-Specific Compiler Settings
   - Synopsys DesignWare-Specific Compiler Settings
   - Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   - Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      | This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   | See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

- JEDEC Files (.jed)
- Programmer Object Files (.pof)
- SRAM Object Files (.sof)
- Hexadecimal (Intel-format) Files (.hex)
- Tabular Text Files (.ttf)

| Refer to the following sources for additional information:

- Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
- Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
- Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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