## Converting Verilog HDL Designs into MAX+PLUS II-
Compatible EDIF Netlist Files with the vlog2alt Utility

You can use the vlog2alt utility to convert your Verilog HDL design into an EDIF netlist file. This file can then be imported into the MAX+PLUS® II software as an EDIF Input File with the extension .edf.

To convert a Verilog HDL design into an EDIF netlist file, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Synthesize and optimize your Verilog HDL design with Synergy, as described in Synthesizing & Optimizing Verilog HDL Files with Synergy Software.

3. To convert your Verilog HDL design into an EDIF netlist file, type the following command at the UNIX prompt from your working directory:

   `vlog2alt <`design name>`-rundir max2 -vfiles` <design name>`.run1/syn.v`

4. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files:

- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Cadence Topics | Synergy Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.