## Updating DesignWare Libraries

Although Altera provides DesignWare libraries that are pre-compiled for the current version of Synopsys tools, you may wish to recompile the libraries.

Altera provides compilable source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare software with any version of the Design Compiler or FPGA Compiler software.They also allow you to install components whose source is written in VHDL, even if you are licensed only for the Verilog HDL Compiler software.

Source files for the Design Compiler software are automatically installed in the following directories:

- /usr/maxplus2/synopsys/library/alt_syn/flex10k/src/dw_flex10k[<speed grade>]
- /usr/maxplus2/synopsys/library/alt_syn/flex8000/src/dw_flex8000[<speed grade>]
- /usr/maxplus2/synopsys/library/alt_syn/flex6000/src/dw_flex6000<speed grade>

Source files for the FPGA Compiler are automatically installed in the following directories:

- /usr/maxplus2/synopsys/library/alt_syn/flex10k/src/dw_flex10k[<speed grade>]_fpga
- /usr/maxplus2/synopsys/library/alt_syn/flex8000/src/dw_flex8000[<speed grade>]_fpga
- /usr/maxplus2/synopsys/library/alt_syn/flex6000/src/dw_flex6000<speed grade>_fpga

You can compile the VHDL source file for use with the appropriate library. Refer to Table 1 to determine which commands you should type at the UNIX prompt to compile the library.

Table 1. Commands for Compiling the Library
Device Family | Synopsys Compiler | Commands for Compiling the Library Note (1)
FLEX®6000 | Design Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex6000/ src/dw_flex6000`<speed grade>`dw_flex6000.script`
FPGA Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex6000/ src/dw_flex6000`<speed grade>`_fpga dw_flex6000.script`
FLEX 8000 | Design Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex8000/ src/dw_flex8000[`<speed grade>`] dw_flex8000.script`
FPGA Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex8000/ src/dw_flex8000[`<speed grade>`]_fpga dw_flex8000.script`
FLEX 10K | Design Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex10k/ src/dw_flex10k[`<speed grade>`] dw_flex10k.script`
FPGA Compiler | `cd /usr/maxplus2/synopsys/library/alt_syn/flex10k/ src/dw_flex10k[`<speed grade>`]_fpga dw_flex10k.script`

Notes:

1. For FLEX 6000 devices, you must specify either `-2` or `-3` for the <speed grade> variable. For FLEX 8000 and FLEX 10K devices, you must specify `-2`, `-3`,`-4`, `-5`, or `-6`; or `-1`, `-2`, `-3`, `-4`, or `-5`; respectively, for the <speed grade> variable.

| Go to the following topics for additional information:

- Setting Up the DesignWare Interface
- Setting Up the MAX+PLUS II/Synopsys Working Environment
- Setting Up Design Compiler & FPGA Compiler Configuration Files
- Setting Up VSS Configuration Files

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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