## Altera-Provided Logic & Symbol Libraries

The MAX+PLUS® II/Viewlogic Powerview environment provides libraries for compiling, synthesizing, and simulating designs.

| You can create your own libraries of custom symbols and logic functions for use in ViewDraw schematics and VHDL design files. You can use custom symbols (and functions) to incorporate an EDIF Input File, TDF, or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the vwlogic.lmf Library Mapping File to map ViewDraw symbols to equivalent MAX+PLUS II megafunctions, macrofunctions, or primitives. To use custom symbols and functions, you can create a custom LMF that maps your custom functions to equivalent EDIF Input Files, TDFs, or other MAX+PLUS II-supported design files. Go to "Library Mapping File" and "Viewlogic Library Mapping File" in MAX+PLUS II Help for more information.

Logic symbols used in ViewDraw software are available from the MAX+PLUS II alt_max2 library, the ViewDraw builtin and 74ls libraries, and the ViewDatapath vdpath library. VHDL models of MAX+PLUS II logic functions are available from the Altera-provided alt_mf library.

### The alt_max2 Library

The alt_max2 library provides MAX+PLUS II-specific logic functions that can be used to take advantage of special architectural features in each Altera® device family. See Table 1. Symbols and functional simulation models are available for all of these elements.

### The alt_mf Library

The Altera-provided alt_mf library, which supports the Viewlogic Vantage VHDL Analyzer software, contains VHDL simulation models for all logic functions listed in the following table. The library is configured so that these functions pass untouched through the EDIF netlist file to the MAX+PLUS II Compiler, providing you with optimal control over design processing. Altera also provides models for all of the logic functions that you can synthesize and simulate. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description.

#### Table 1. Architecture Control Logic Functions

Name Note (1), Note (2) | Description | Name | Description | Name | Description
--- | --- | --- | --- | --- | ---
`8fadd` | 8-bit full adder macrofunction | `LCELL` | Logic cell buffer primitive | `EXP` | MAX® 5000, MAX 7000, and MAX 9000 Expander buffer primitive
`8mcomp` | 8-bit magnitude comparator macrofunction | `GLOBAL` | Global input buffer primitive | `SOFT` | Soft buffer primitive
`8count` | 8-bit up/down counter macrofunction | `CASCADE` | FLEX® 6000, FLEX 8000, and FLEX 10K cascade buffer primitive | `OPNDRN` | Open-drain buffer primitive
`81mux` | 8-to-1 multiplexer macrofunction | `CARRY` | FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer primitive | `DFFE` Note (2) | D-type flipflop with Clock Enable primitive
`clklock` | Phase-locked loop megafunction |  |  |  |

Notes:

1. Logic function names that begin with a number must be prefixed with "`a_`" in VHDL designs. For example, `8fadd` must be specified as `a_8fadd`.
2. For designs that are targeted to FLEX 6000 devices, you should use the `DFFE` primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the `DFFE6K` primitive.

| Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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