## Analyzing VHDL Files with the SpeedWave VHDL Analyzer Software

You can use the SpeedWave VHDL Analyzer software to analyze VHDL Design Files (.vhd) prior to functional (or gate-level) simulation with ViewSim software, or to synthesis and optimization with ViewSynthesis software. You can also use the SpeedWave VHDL Analyzer to analyze a MAX+PLUS® II-generated VHDL Output File (.vho) prior to post-compilation timing simulation with ViewSim software. The max2_VantgMgr and max2_VantgAnlz tools are located in the Altera® Toolbox Design Tools Drawer.

To analyze a VHDL file with the SpeedWave VHDL Analyzer, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. If you wish to analyze a VHDL Design File (.vhd), create a VHDL file <design name>.vhd using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software for more information.

3. If you wish to analyze a MAX+PLUS II-generated VHDL Output File (.vho), be sure to select VHDL 1987 for the VHDL Version option and VHDL Output File (.vho) for the Write Delay Constructs To option in the VHDL Netlist Writer Settings dialog box (Interfaces menu) when you set up the MAX+PLUS II Compiler to generate a VHDL Output File. See Compiling Projects with MAX+PLUS II Software for more information on generating VHDL Output Files.

4. If your VHDL file contains functions from the alt_mf library, follow these steps:

   1. Start the Vantage Manager by double-clicking Button 1 on the max2_VantgMgr icon in the Design Tools Drawer.

   2. Use the Vantage VHDL Library Manager to create an alt_mf.lib library file with the symbolic name `ALT_MF`.

   3. Make alt_mf the working library with the Set Working command (Edit menu).

   4. Start the VHDL Analyzer by double-clicking Button 1 on the max2_VantgAnlz icon in the Design Tools Drawer.

   5. Analyze each VHDL file in the alt_mf/src directory into the alt_mf.lib working library. Source files are located in the /usr/maxplus2/vwlogic/library/alt_mf/src directory that is created by installing the Altera/Viewlogic interface.

5. If it is not already running, start the Vantage VHDL Library Manager, as described in step 4b, to create a Vantage library.

6. Choose the List system libs button.

7. Add the ieee.lib and synopsys.lib system libraries to your project:

   1. Select the ieee.lib and synopsys.lib libraries from the Available Libraries window and choose Add lib. Choose the ieee library from the libs_syn directory, which is located at /<Powerview system directory>/ standard/van_vss/pgm/libs_syn. The ieee library contains Synopsys package files.

   2. If your project uses functions from the alt_mf library, also select the alt_mf.lib file from the Available Libraries window and choose Add lib.

   3. Choose Create Library (File menu, type the project directory name in the Symbolic Name field, and choose OK.

8. Specify the project directory as the working directory by choosing Set Working (Edit menu).

9. Choose Save INI File (File menu).

10. Choose Dismiss Window (Powerview Red-Box menu).

11. Specify the appropriate path and file name in the Analyzer VHDL Source File dialog box and choose OK to analyze the VHDL file.

12. Once you have analyzed the file, perform one or more of the following tasks, as appropriate:

    - Performing a Functional Simulation with ViewSim Software
    - Synthesizing & Optimizing VHDL Designs with ViewSynthesis Software
    - Performing a Timing Simulation with ViewSim Software

| Refer to the following sources for related information:

- The Viewlogic ViewSim/VHDL User's Guide and ViewSim/VHDL Tutorial for information on using the Vantage VHDL Analyzer software or Vantage VHDL Library Manager
- Powerview Command-Line Syntax in these MAX+PLUS II ACCESSSM Key topics

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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