## Using Viewlogic SpeedWave VHDL Analyzer & MAX+PLUS II Software

The following topics describe how to use the Viewlogic SpeedWave VHDL Analyzer software with MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment

- Software Requirements
- MAX+PLUS II/Viewlogic Powerview Interface File Organization
- Viewlogic Powerview viewdraw.ini Configuration File
- MAX+PLUS II/Viewlogic Powerview Project File Structure
- Altera-Provided Logic & Symbol Libraries
- The vdpath & mega_lpm Libraries

### VHDL Design Entry

- Design Entry Flow
- Creating VHDL Designs for Use with MAX+PLUS II Software
  - Instantiating the clklock Megafunction in VHDL or Verilog HDL
  - Instantiating RAM & ROM Functions in Viewlogic Powerview Designs
- Entering Resource Assignments
  - Modifying the Assignment & Configuration File with the setacf Utility

### VHDL Analysis

- Analyzing VHDL Files with the SpeedWave VHDL Analyzer Software

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Powerview Command-Line Syntax
- Performing a Functional Simulation with ViewSim Software
- Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
- Performing a Timing Simulation with ViewSim Software
- Compiling Projects with MAX+PLUS II Software
- Programming Altera® Devices

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Viewlogic web site (http://www.Viewlogic.com)

## Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment

To use the MAX+PLUS® II software with Viewlogic's Powerview software, you must install the MAX+PLUS II software, familiarize yourself with the Altera® Toolbox in the Powerview Cockpit, and then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Viewlogic Powerview interface is installed automatically when you install the MAX+PLUS II software on your workstation.

To set up your working environment for the MAX+PLUS II/Viewlogic Powerview interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Viewlogic software versions described in MAX+PLUS II/Viewlogic Powerview Software Requirements.

2. Add the following environment variable to your .cshrc file to specify /usr/maxplus2 as the MAX+PLUS II system directory:

   `setenv ALT_HOME /usr/maxplus2`

3. Add the $ALT_HOME/Viewlogic/standard, $ALT_HOME/bin, and $ALT_HOME/Viewlogic/bin directories to the `PATH` environment variable in your .cshrc file.

4. Add the $ALT_HOME/Viewlogic/standard directory to the `WDIR` environment variable in your .cshrc file using the following syntax:

   `setenv WDIR $ALT_HOME/Viewlogic/standard:/<`Powerview system directory>`/standard`

   | Make sure the $ALT_HOME/Viewlogic/standard directory is the first directory in your `WDIR` path.

5. Source your .cshrc file by typing `source .cshrc` at the UNIX prompt.

6. Create the Viewlogic Powerview viewdraw.ini configuration file.

7. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:

   `cp /usr/maxplus2/maxplus2.ini $HOME`

   `chmod u+w $HOME/maxplus2.ini`

   | The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as MAX+PLUS II symbol and logic function library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.

   Normally, you do not have to edit your local copy of maxplus2.ini, because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

8. If you plan to instantiate Library of Parameterized Modules (LPM) functions in ViewDraw schematics, you must create a new file with the name vdraw.vs. The vdraw.vs file must include the following line:

   `load ("vdpath")`

   You must also make sure that you specify the vdraw.vs file in your `WDIR` path.

9. Set up a directory structure that facilitates working with the MAX+PLUS II/Viewlogic Powerview interface. Refer to MAX+PLUS II/Viewlogic Powerview Project File Structure.

| Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Viewlogic Powerview Interface File Organization for information about the MAX+PLUS II/Viewlogic Powerview directories that are created during MAX+PLUS II installation.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Viewlogic Software Requirements

The following applications and utilities are used to generate, process, synthesize, and verify a project with MAX+PLUS® II and Viewlogic software.

Viewlogic | Altera
--- | ---
VHDL Analyzer | ViewTrace | MAX+PLUS II version 10.0
Vantage VHDL Analyzer | ViewData Path |
VHDL -> sym | MOTIVE version 5.1.6 |
edifneto | SDF2MTV (optional) |
edifneti | Fusion/VCS |
EEDIF (optional) | vsm |
MMP (optional) | ViewPath (optional) |

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Viewlogic applications the current version of the MAX+PLUS II software supports. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

## MAX+PLUS II/Viewlogic Powerview Interface File Organization

Table 1 shows the MAX+PLUS® II/Viewlogic Powerview interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation.

| For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

#### Table 1. MAX+PLUS II Directory Organization

Directory | Description
--- | ---
./lmf | Contains the Altera-provided Library Mapping File, vwlogic.lmf, that maps Viewlogic logic functions to equivalent MAX+PLUS II logic functions.
./Viewlogic | Contains the alt_edif.cfg EDIF configuration file that is used with the edifneti utility. Also contains the library and sample subdirectories.
./Viewlogic/examples | Contains the sample Viewlogic designs.
./Viewlogic/library/max2sim | Contains the MAX+PLUS II simulation model library (max2_sim) for use in ViewSim software.
./Viewlogic/library/alt_max2 | Contains MAX+PLUS II primitives (`EXP`, `GLOBAL`, `LCELL`, `SOFT`, `CARRY`, `CASCADE`, `DFFE`, `DFFE6K`, and `OPNDRN`), macrofunctions (`a_8fadd`, `a_8mcomp`, `a_8count`, `a_81mux`), and megafunctions (`clklock`) for use in ViewDraw schematics. These logic functions support specific architectural features of Altera® devices. The alt_max2 library also contains modified versions of the ViewDraw primitives that use tri-state buffers, because these primitives require special handling in the MAX+PLUS II/Viewlogic Powerview interface.
./Viewlogic/library/synlib | Contains the Altera-provided synthesis library altera, which includes MAX+PLUS II primitives, the altera.sml file, a sym directory, and a wir directory for use with ViewSynthesis software.
./Viewlogic/library/alt_mf | Contains the VHDL models for the MAX+PLUS II primitives (`EXP`, `GLOBAL`, `LCELL`, `SOFT`, `CARRY`, `CASCADE`, `DFFE`, and `OPNDRN`), macrofunctions (`clklock`) for use with ViewSynthesis software, the Vantage VHDL Analyzer software, and the VHDL source files. These logic functions are used to maintain portability to other architectures.
./Viewlogic/library/alt_time | Contains MOTIVE timing models for MAX+PLUS II logic functions (motive.lib), including the `clklock` megafunction, and MAX+PLUS II driver models (motive.drv).
./Viewlogic/library/alt_vtl | Contains the VHDL source files for the VITAL 3.0-compliant library. This library is available for ViewSim software.
./Viewlogic/bin | Contains all MAX+PLUS II, Viewlogic, and interface-related scripts.
./Viewlogic/standard | Contains all standard .ini files and standard tools.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## Viewlogic Powerview viewdraw.ini Configuration File

Each Powerview project is configured with the viewdraw.ini file that resides in the project directory. The `DIR` statements at the end of viewdraw.ini are paths to library directories that are used by the various Powerview applications. Figure 1 shows a sample of the `DIR` statements that are required to use the libraries.

#### Figure 1. Excerpt from viewdraw.ini

`DIR [pw]` | `.`
`DIR [r]` | `/usr/maxplus2/vwlogic/library/alt_max2 (alt_max2)`
`DIR [r]` | `/usr/maxplus2/vwlogic/library/max2sim (max2_sim)`
`DIR [r]` | `/usr/maxplus2/vwlogic/library/synlib (altera)`
`DIR [r]` | `/usr/maxplus2/vwlogic/library/alt_mf (alt_mf)`
`DIR [r]` | `/usr/maxplus2/vwlogic/library/alt_vtl (alt_vtl)`
`DIR [rm]` | `/`<Powerview system directory>`/lib/builtin (builtin)`
`DIR [rm]` | `/`<Powerview system directory>`/simmods/vl/dip/74ls (vl74ls)`
`DIR [rm]` | `/`<Powerview system directory>`/symsets/vl/dip/74ls (vl74ls)`
`DIR [r]` | `/`<Powerview system directory>`/lib/vdpath (vdpath)`

| When you add the libraries to the /usr/maxplus2/vwlogic/standard/viewdraw.ini file, they are automatically set when you create a new project. Powerview tools search these libraries sequentially, so it is important to add them in the order in which they are listed in Figure 1.

Table 1 shows the libraries that must be specified in the `DIR` statements in the viewdraw.ini file.

#### Table 1. Powerview Application Libraries

Library | Library Alias | Source | Topics
--- | --- | --- | ---
alt_max2 | `alt_max2` | Altera | Graphical elements for ViewDraw
max2sim | `max2_sim` | Altera | Models for project simulation
synlib | `altera` | Altera | VHDL synthesis library for the MAX+PLUS® II software
alt_mf | `alt_mf` | Altera | VHDL models of MAX+PLUS II logic functions
alt_vtl | `alt_vtl` | Altera | VITAL-compliant primitives
builtin | `builtin` | Altera | Basic primitives such as `INPUT` pins, `OUTPUT` pins, `AND` gates, `OR` gates, etc.
74ls | `vl74ls` | Viewlogic | 74-series macrofunctions
vdpath | `vdpath` | Viewlogic | Standard library of parameterized modules (LPM) functions

| The Altera-provided libraries must be listed before the Viewlogic-provided libraries in the viewdraw.ini file to ensure that the correct versions of the megafunctions, macrofunctions, and primitives are used.

| Go to Altera-Provided Logic & Symbol Libraries for more information on Altera-supplied libraries. Refer to the Powerview documentation for more information on setting up the viewdraw.ini file.

## MAX+PLUS II/Viewlogic Powerview Project File Structure

In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an Altera® Hardware Description Language (AHDL) TDF; or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by Powerview and imported into the MAX+PLUS II software as an EDIF Input File (.edf). Figure 1 shows an example of MAX+PLUS II project directory structure that includes Powerview-generated files.

#### Figure 1. Sample MAX+PLUS II Project Organization

The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

Unlike Powerview, the MAX+PLUS II software does not automatically create a project directory when you create a project. A single directory can contain several MAX+PLUS II design files, and you can specify any one of the designs in the directory as a project in the MAX+PLUS II software.

### Viewlogic Powerview Local Work Area Structure

When you create a project with the Powerview Cockpit's Create command (Project menu), the project directory is created. You should generate design files and functional simulation files under this directory. A max2 subdirectory is automatically created under your current project directory when you generate an EDIF file from your schematic or VHDL file. The <project name>.edf file is stored in the max2 subdirectory. All MAX+PLUS® II Compiler output files are created in the /<project name>/max2 subdirectory.

| ViewDraw files are identified by their directories and not by their extensions, so it is easy to overwrite files unintentionally. To avoid overwriting files, Altera recommends that you create a new project directory, <project name>/max2/sim, where you can generate all the files needed for simulation.

### ViewDraw Project File Structure

Each ViewDraw project directory contains three subdirectories: wir, sch, and sym. See Table 1.

#### Table 1. ViewDraw Subdirectories

Directory | Topics
--- | ---
./wir | Wirelist files that contain connectivity information for a particular logic block
./sch | Schematics that contain logic
./sym | Symbol files that are the ViewDraw graphical representation of the logic blocks

Each file type uses the filename extension .1. Different file types are distinguished only by their directory: /lib/wir/<project name>.1 is a wirelist file; /lib/sch/<project name>.1 is the corresponding schematic file; and /lib/sym/<project name>.1 is the corresponding symbol.

### VHDL Project File Structure

Each VHDL project directory contains three subdirectories. See Table 2.

#### Table 2. VHDL Subdirectories

Directory | Topics
./synth | All synthesis-related files and directories
./synth/<entity> | Four types of files: <entity>.pdf, <entity>.opt, <entity>.sta, and <entity>.gnl
./wir | Wirelist for synthesized VHDL modules

| For each VHDL entity in the design, there is a corresponding ./synth/<entity> directory.

## Altera-Provided Logic & Symbol Libraries

The MAX+PLUS® II/Viewlogic Powerview environment provides libraries for compiling, synthesizing, and simulating designs.

| You can create your own libraries of custom symbols and logic functions for use in ViewDraw schematics and VHDL design files. You can use custom symbols (and functions) to incorporate an EDIF Input File, TDF, or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the vwlogic.lmf Library Mapping File to map ViewDraw symbols to equivalent MAX+PLUS II megafunctions, macrofunctions, or primitives. To use custom symbols and functions, you can create a custom LMF that maps your custom functions to equivalent EDIF Input Files, TDFs, or other MAX+PLUS II-supported design files. Go to "Library Mapping File" and "Viewlogic Library Mapping File" in MAX+PLUS II Help for more information.

Logic symbols used in ViewDraw software are available from the MAX+PLUS II alt_max2 library, the ViewDraw builtin and 74ls libraries, and the ViewDatapath vdpath library. VHDL models of MAX+PLUS II logic functions are available from the Altera-provided alt_mf library.

### The alt_max2 Library

The alt_max2 library provides MAX+PLUS II-specific logic functions that can be used to take advantage of special architectural features in each Altera® device family. See Table 1. Symbols and functional simulation models are available for all of these elements.

### The alt_mf Library

The Altera-provided alt_mf library, which supports the Viewlogic Vantage VHDL Analyzer software, contains VHDL simulation models for all logic functions listed in the following table. The library is configured so that these functions pass untouched through the EDIF netlist file to the MAX+PLUS II Compiler, providing you with optimal control over design processing. Altera also provides models for all of the logic functions that you can synthesize and simulate. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description.

#### Table 1. Architecture Control Logic Functions

Name Note (1), Note (2) | Description | Name | Description | Name | Description
--- | --- | --- | --- | --- | ---
`8fadd` | 8-bit full adder macrofunction | `LCELL` | Logic cell buffer primitive | `EXP` | MAX® 5000, MAX 7000, and MAX 9000 Expander buffer primitive
`8mcomp` | 8-bit magnitude comparator macrofunction | `GLOBAL` | Global input buffer primitive | `SOFT` | Soft buffer primitive
`8count` | 8-bit up/down counter macrofunction | `CASCADE` | FLEX® 6000, FLEX 8000, and FLEX 10K cascade buffer primitive | `OPNDRN` | Open-drain buffer primitive
`81mux` | 8-to-1 multiplexer macrofunction | `CARRY` | FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer primitive | `DFFE` Note (2) | D-type flipflop with Clock Enable primitive
`clklock` | Phase-locked loop megafunction |  |  |  |

Notes:

1. Logic function names that begin with a number must be prefixed with "`a_`" in VHDL designs. For example, `8fadd` must be specified as `a_8fadd`.
2. For designs that are targeted to FLEX 6000 devices, you should use the `DFFE` primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the `DFFE6K` primitive.

| Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

## The vdpath & mega_lpm Libraries

The library of parameterized modules (LPM) 2.1.0 standard defines a set of parameterized functions and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. After the design is completed, you can target the design to any device family.

When the MAX+PLUS® II software processes projects that include Viewlogic-provided vdpath LPM functions, it uses functions from the Altera-provided mega_lpm library. This library includes all standard LPM functions except the truth table, finite state machine, and pad functions. Altera does not directly support the `lpm_ram_dq`, `lpm_ram_io`, and `lpm_rom` functions. Refer to Instantiating RAM & ROM Functions in Viewlogic Powerview Designs for instructions on instantiating RAM and ROM functions.

| Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions.

## MAX+PLUS II/Viewlogic Powerview Design Entry Flow

Figure 1 shows the design entry flow for the MAX+PLUS® II/Viewlogic Powerview interface.

#### Figure 1. MAX+PLUS II/Viewlogic Powerview Design Entry Flow

| Altera-provided items are shown in blue.

## Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL design that can be synthesized and optimized with ViewSynthesis software, follow these steps:

1. You can instantiate the following Altera-provided logic functions in your VHDL design:

   - The alt_mf library contains the Altera® VHDL logic function library, which includes MAX+PLUS II-specific primitives and the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` macrofunctions. If you wish to instantiate alt_mf logic functions in your VHDL design, you must first analyze all functions in the alt_mf/src directory. See Analyzing VHDL Files with the Vantage VHDL Analyzer Software for details.

   - The `clklock` megafunction, which enables the phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for information.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. (Optional) To enter resource assignments in your VHDL design, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.

Once you have created a VHDL design, you can analyze it, synthesize it, and generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:

- You can analyze, functionally simulate, and synthesize the VHDL design, then generate an EDIF netlist file by following the steps in these topics:

  - Analyzing VHDL Files with the Vantage VHDL Analyzer Software
  - Performing a Functional Simulation with ViewSim Software
  - Synthesizing & Optimizing VHDL Designs with ViewSynthesis Software
  - Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility

- You can use the VHDL <-> max2 utility in the Max2 Express Drawer to automatically analyze and synthesize the VHDL design, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and create a .vsm file for simulation. See Using the Max2 Express Drawer's VHDL <-> max2 Utility in these MAX+PLUS II ACCESSSM Key topics for details.

Installing the Altera-provided MAX+PLUS II/Viewlogic Powerview interface on your computer automatically creates the following sample VHDL files:

- /usr/maxplus2/examples/Viewlogic/example5/count4.vhd
- /usr/maxplus2/examples/Viewlogic/example5/count8.vhd

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating the clklock Megafunction in VHDL or Verilog HDL

MAX+PLUS® II interfaces to other EDA tools support the `clklock` phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility, which is available in the MAX+PLUS II system directory. Type `gencklk -h` at the DOS or UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).

The gencklk utility allows parameters for the `clklock` function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the `clklock` function name; therefore, the values do not need to be declared explicitly.

To instantiate the `clklock` megafunction in VHDL or Verilog HDL, go through the following steps:

1. Type the following command at the DOS or UNIX prompt to generate the `clklock_`x`_`y function, where x is the ClockBoost™ value and y is the input frequency in MHz:

   | Type `gencklk` <ClockBoost> <input frequency>`-vhdl` for VHDL designs.

   or:

   | Type `gencklk` <ClockBoost> <input frequency> `-verilog` for Verilog HDL designs.

   Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the `clklock` megafunction.

2. Create a design file that instantiates the `clklock``_`x`_`y.vhd or `clklock`_x_y.v file. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.

| In MAX+PLUS II version 8.3 and lower, running `genclklk` on a PC always creates files named as clklock.vhd, clklock.cmp, and clklock.v, regardless of the ClockBoost and input frequency values you specify.

Figures 1 and 2 show a `clklock` function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.

Figure 1. VHDL Design File with clklock Instantiation (count8.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY altera;
    USE altera.maxplus2.all;     --  Include Altera Component Declarations
    ENTITY count8 IS
       PORT (a    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             ldn  : IN STD_LOGIC;
             gn   : IN STD_LOGIC;
             dnup : IN STD_LOGIC;
             setn : IN STD_LOGIC;
             clrn : IN STD_LOGIC;
             clk  : IN STD_LOGIC;
             co   : OUT STD_LOGIC;
             q    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END count8;
    ARCHITECTURE structure OF count8 IS
       signal clk2x : STD_LOGIC;
    COMPONENT clklock_2_40
       PORT (
          INCLK : IN STD_LOGIC;
          OUTCLK : OUT STD_LOGIC
       );
    END COMPONENT;
    BEGIN
       u1: clklock_2_40
       PORT MAP (inclk=>clk, outclk=>clk2x);
       u2: a_8count
       PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
                 e=>a(4), f=>a(5), g=>a(6), h=>a(7),
                 clk=>clk2x,
                 ldn=>ldn,
                 gn=>gn,
                 dnup=>dnup,
                 setn=>setn,
                 clrn=>clrn,
                 qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
                 qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
                 cout=>co);
     END structure;

Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v)
    `timescale 1ns / 10ps
    module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q);
    output          co;
    output[7:0]     q;
    input[7:0]      a;
    input           ldn, gn,dnup, setn, clrn, clk;
    wire            clk2x;
    clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) );
    A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]),
                 .G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
                 .SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
                 .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
                 .QH(q[7]), .COUT(co) );
    endmodule

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating RAM & ROM Functions in Viewlogic Powerview Designs

The MAX+PLUS®II/Viewlogic Powerview interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual-port RAM, dual-port RAM, single-Clock FIFO, and dual-Clock FIFO functions. You can use the Altera-provided genmem utility to generate functional simulation models and timing models for these functions. Type `genmem` at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate. RAM and ROM can be instantiated in both ViewDraw schematics and VHDL designs.

| Refer to Viewlogic documentation for information on simulating projects that contain RAM functions. The procedure for reading an EDIF Output File and preparing it for simulation with ViewSim requires additional steps when the project contains RAM functions.

When you instantiate a RAM or ROM function, follow these general guidelines:

- For ROM functions, you must specify an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format. The filename must be the same as the instance name; e.g., the instance name must be unique throughout the whole project, and must contain only valid name characters. The initialization file must reside in the directory containing the project's design files.

- For RAM functions, specifying a memory initialization file is optional.

- For VHDL designs, specify the name of the initial memory content file in the Generic Map Clause of the instance, with the specified type `LPM_FILE`. If you do not use an initial memory content file (e.g., for a RAM function), you should not declare or use the Generic Clause.

- Do not synthesize the genmem-generated VHDL file: it is intended for simulation only.

| The MIF format is supported only for specifying initial memory content when compiling designs within the MAX+PLUS II software. You cannot use a MIF to perform simulation with Viewlogic tools prior to MAX+PLUS II compilation.

To instantiate RAM or ROM in a ViewDraw schematic, follow these steps:

1. Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:

   `genmem` <memory type>`` <memory size>`-vwlogic`

   For example: `genmem asynrom 256x15 -vwlogic`

2. Start the VHDL-to-symbol utility, vhdl2sym, by double-clicking Button 1 on the max2_vhdl2sym icon in the Altera® Toolbox Design Tools Drawer.

3. Specify the following options in the vhdl2sym dialog box and choose OK to create a symbol. For example, to create the symbol for a 256x15 asynchronous ROM, enter the following settings:

   Option: | Setting:
   --- | ---
   VHDL Source Filename | asyn_rom_256x15.vhd
   Add LEVEL attribute | On

4. Choose Comp (Add menu), type <design name> in the Enter Name box, and choose OK.

To instantiate a RAM or ROM function in VHDL, follow these steps:

1. Repeat step 1 above.
2. Create a VHDL design that incorporates the text from the genmem-generated Component Declaration, <memory name>.cmp, and instantiate the <memory name> function.

Figure 1 shows a VHDL design that instantiates asyn_rom_256x15.vhd, a 256 x 15 ROM function.

Figure 1. VHDL Design File with ROM Instantiation (tstrom.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY tstrom IS
            PORT (
              addr    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
              memenab : IN STD_LOGIC;
              q       : OUT STD_LOGIC_VECTOR (14 DOWNTO 0));
    END tstrom;
    ARCHITECTURE behavior OF tstrom IS

    COMPONENT asyn_rom_256x15
         GENERIC (LPM_FILE : string);
         PORT (Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               MemEnab : IN STD_LOGIC;
               Q       : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
         );
    END COMPONENT;
    BEGIN

       u1: asyn_rom_256x15
            GENERIC MAP (LPM_FILE => "u1.hex")
       PORT MAP (Address => addr, MemEnab => memenab, Q =>q);
    END behavior;

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In the MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor.

### ViewDraw Schematics

In ViewDraw schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File (.edf) into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility

Installing the Altera-provided MAX+PLUS II/Viewlogic interface on your computer automatically creates the following sample ViewDraw schematic file, which includes resource assignments:

- /usr/maxplus2/examples/Viewlogic/example4/fadd2mpp

| Go to Viewlogic documentation for information on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in ViewDraw.

### VHDL Design Files

For VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility.

| For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## Analyzing VHDL Files with the SpeedWave VHDL Analyzer Software

You can use the SpeedWave VHDL Analyzer software to analyze VHDL Design Files (.vhd) prior to functional (or gate-level) simulation with ViewSim software, or to synthesis and optimization with ViewSynthesis software. You can also use the SpeedWave VHDL Analyzer to analyze a MAX+PLUS® II-generated VHDL Output File (.vho) prior to post-compilation timing simulation with ViewSim software. The max2_VantgMgr and max2_VantgAnlz tools are located in the Altera® Toolbox Design Tools Drawer.

To analyze a VHDL file with the SpeedWave VHDL Analyzer, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. If you wish to analyze a VHDL Design File (.vhd), create a VHDL file <design name>.vhd using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software for more information.

3. If you wish to analyze a MAX+PLUS II-generated VHDL Output File (.vho), be sure to select VHDL 1987 for the VHDL Version option and VHDL Output File (.vho) for the Write Delay Constructs To option in the VHDL Netlist Writer Settings dialog box (Interfaces menu) when you set up the MAX+PLUS II Compiler to generate a VHDL Output File. See Compiling Projects with MAX+PLUS II Software for more information on generating VHDL Output Files.

4. If your VHDL file contains functions from the alt_mf library, follow these steps:

   1. Start the Vantage Manager by double-clicking Button 1 on the max2_VantgMgr icon in the Design Tools Drawer.

   2. Use the Vantage VHDL Library Manager to create an alt_mf.lib library file with the symbolic name `ALT_MF`.

   3. Make alt_mf the working library with the Set Working command (Edit menu).

   4. Start the VHDL Analyzer by double-clicking Button 1 on the max2_VantgAnlz icon in the Design Tools Drawer.

   5. Analyze each VHDL file in the alt_mf/src directory into the alt_mf.lib working library. Source files are located in the /usr/maxplus2/vwlogic/library/alt_mf/src directory that is created by installing the Altera/Viewlogic interface.

5. If it is not already running, start the Vantage VHDL Library Manager, as described in step 4b, to create a Vantage library.

6. Choose the List system libs button.

7. Add the ieee.lib and synopsys.lib system libraries to your project:

   1. Select the ieee.lib and synopsys.lib libraries from the Available Libraries window and choose Add lib. Choose the ieee library from the libs_syn directory, which is located at /<Powerview system directory>/ standard/van_vss/pgm/libs_syn. The ieee library contains Synopsys package files.

   2. If your project uses functions from the alt_mf library, also select the alt_mf.lib file from the Available Libraries window and choose Add lib.

   3. Choose Create Library (File menu, type the project directory name in the Symbolic Name field, and choose OK.

8. Specify the project directory as the working directory by choosing Set Working (Edit menu).

9. Choose Save INI File (File menu).

10. Choose Dismiss Window (Powerview Red-Box menu).

11. Specify the appropriate path and file name in the Analyzer VHDL Source File dialog box and choose OK to analyze the VHDL file.

12. Once you have analyzed the file, perform one or more of the following tasks, as appropriate:

    - Performing a Functional Simulation with ViewSim Software
    - Synthesizing & Optimizing VHDL Designs with ViewSynthesis Software
    - Performing a Timing Simulation with ViewSim Software

| Refer to the following sources for related information:

- The Viewlogic ViewSim/VHDL User's Guide and ViewSim/VHDL Tutorial for information on using the Vantage VHDL Analyzer software or Vantage VHDL Library Manager
- Powerview Command-Line Syntax in these MAX+PLUS II ACCESSSM Key topics

## Powerview Command-Line Syntax

Table 1 shows the command-line syntax for using Powerview functions.

#### Table 1. Powerview Command-Line Syntax

Action | Command
--- | ---
Start VHDL Analyzer software | `vhdl -v` <project name>
Start ViewSynthesis software | `vhdldes`
Load Altera® technology library | `vhdldes> technology altera`
Compile a VHDL design | `vhdldes> vhdl` <project name>
Synthesize a design | `vhdldes> synthesize`
Generate wirelist file | `vhdldes> wir`
Create a schematic representation | `vhdldes> viewgen`
Generate a synthesis report file | `vhdldes> report`
Start the graphical user interface for ViewSynthesis | `vhdldes> vdesgui`
Start the VHDL-to-symbol utility | `vhdl2sym` <project name>
Start vsm | `vsm` <project name>
Start ViewSim simulator | `viewsim` <project name> -<project name>`.cmd`
Start edifneto | `edifneto -f` <project name>-`l` (`std` or `altera`) <project name>`.edf`
Start Vantage VHDL Analyzer software | `analyze -src` <design file>
Start MOTIVE for Powerview software | `mfp`

## Performing a Functional Simulation with ViewSim Software

You can use Viewlogic ViewSim software to perform a functional simulation of a ViewDraw schematic or a VHDL Design File (.vhd) before compiling your project with the MAX+PLUS II Compiler. Follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Create a ViewDraw schematic that follows the guidelines in Creating ViewDraw Schematics for Use with MAX+PLUS II Software. Then go to step 3.

   or:

   Create a VHDL Design File <design name>.vhd and analyze it, as described in the following MAX+PLUS II ACCESSSM Key topics:

   - Creating VHDL Designs for Use with MAX+PLUS II Software
   - Analyzing VHDL Files with the Vantage VHDL Analyzer Software

   Then go to step 7.

3. With the schematic open in the ViewDraw editor, add `CLR` and `PRE` inputs to any flipflops in your design, or tie the `CLR` and `PRE` ports of the flipflops to VCC. (Use the `PWR` primitive from the builtin library.)

4. Choose Write To (File menu) and save the schematic as <design name>_funct.

5. Start the vsm utility by double-clicking Button 1 on the max2_vsmnet icon in the Altera® Toolbox Design Tools Drawer.

6. Specify the following options in the vsm dialog box and choose OK to generate the <design name>_funct.vsm file:

   Option: | Setting: |
   Design Name | <design name>_funct |
   Level |  | (blank)

7. Create a simulation command file (.cmd) for simulation with ViewSim software. Alternatively, you can enter commands at the prompt in the ViewSim window. Refer to your Viewlogic documentation for more information on creating ViewSim command files.

8. Start the ViewSim simulation tool by double-clicking Button 1 on the max2_VSim icon in the Design Tools Drawer.

9. If you wish to simulate a ViewDraw schematic, specify the following options in the ViewSim dialog box, then go to step 11.

   Option: | Setting:
   Design Name | <design name>_funct
   Command File | <design name>_funct.cmd
   VHDL Source Window | OFF
   VHDL Debugging | OFF

10. If you wish to simulate a VHDL design, specify the following options in the ViewSim dialog box:

    Option: | Setting:
    Design Name | <design name>
    Command File | <design name>.cmd
    Graphical Interface | ON
    VHDL Source Window | OFF or ON
    VHDL Debugging | OFF or ON

11. Choose OK to simulate the design. ViewSim software simulates the design and starts the ViewTrace waveform editor to allow you to observe the simulation results.

12. Use the edifneto utility to generate an EDIF Netlist File (.edf) that can be imported into the MAX+PLUS II software, as described in Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility.

| Go to ViewSim documentation for complete details on simulating a project and using ViewTrace to observe waveform output results.

## Performing a Timing Simulation with ViewSim Software

After you have entered a design and compiled it with the MAX+PLUS® II Compiler, you can simulate a MAX+PLUS II-generated EDIF Output File (.edo) or VHDL Output File (.vho) with ViewSim software. ViewSim software can simulate both the functionality and the timing of your design. It also checks setup time, hold time, and Clock duty cycle timing requirements on registers.

To simulate a design with ViewSim software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Compile the design with the MAX+PLUS II software and generate an EDIF Output File (.edo) or VHDL Output File (.vho), as described in Compiling Projects with MAX+PLUS II Software.

3. In the Viewlogic Cockpit window, choose Create (Project menu) to open the Create Project dialog box. Type the name of your working directory and choose OK. You must create this new directory to avoid overwriting your original files when you generate new files for simulation.

4. Choose SearchOrder (Project menu) and add the appropriate directories and aliases to your viewdraw.ini file if you have not already done so. Go to Viewlogic Powerview viewdraw.ini Configuration File for more information.

   | Refer to Viewlogic documentation for information on simulating projects that contain RAM functions. The procedure for reading an EDIF Output File and preparing it for simulation with ViewSim requires additional steps when the project contains RAM functions.

5. If you used the SCH <-> max2 or VHDL <-> max2 utility in the Max2 Express drawer to process your project, skip to step 8.

6. If you wish to simulate a VHDL Output File, follow the steps in Analyzing VHDL Files with the Vantage VHDL Analyzer then skip to step 7d.

7. If you are using the Altera® Toolbox Design Tools Drawer, follow these steps:

   1. To generate a Powerview wirelist from the EDIF Output File, double-click Button 1 on the max2_edifi icon in the Design Tools Drawer. The Netlist In dialog box is displayed.

   2. In the Netlist In dialog box, specify ../<design name> for the EDIF Netlist File option, then choose OK to process the EDIF netlist file.

   3. If your project is implemented in multiple devices, repeat steps a and b for each EDIF Output File generated by the MAX+PLUS II Compiler, and ensure that the Altera-provided alt_edif.cfg file is specified for the Attribute Swap Configuration File option. In a multi-device project, the MAX+PLUS II Compiler generates a separate file for each device, plus a top-level file that is identified by "_t" appended to the project name. You must also follow the steps in Using ViewDraw & ViewGen Software to Prepare for Multi-Device Board-Level Simulation with ViewSim Software.

   4. Start the vsm utility by double-clicking Button 1 on the max2_vsmnet icon in the Design Tools Drawer.

   5. Specify your design name for the Design Name option in the vsm dialog box and choose OK to generate the <design name>.vsm file.

8. Create a simulation command file (.cmd) for simulation with ViewSim software. Alternatively, you can enter commands at the prompt in the ViewSim window. Refer to your Viewlogic documentation for more information on creating ViewSim command files.

   | The Altera simulation model library, max2_sim, allows you to use the `alt_grst` signal to asynchronously clear all flipflops (`DFFE` primitives).

9. Start the ViewSim simulation tool by double-clicking Button 1 on the max2_VSim icon in the Design Tools Drawer or the Max2 Express Drawer.

10. Specify the following options in the ViewSim dialog box and choose OK to simulate the design:

    Option: | Setting:
    Design Name | <design name>
    Command File | <design name>.cmd
    VHDL Source Window | OFF
    VHDL Debugging | OFF

    ViewSim software simulates the design and starts the ViewTrace waveform editor to allow you to observe the simulation results.

| Refer to the following sources for related information:

- ViewSim documentation for complete details on simulating a project and using ViewTrace to observe waveform output results
- Using ViewDraw & ViewGen Software to Prepare for Multi-Device Board-Level Simulation with ViewSim Software

## Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

| Refer to the following sources for additional information:

- Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

- Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   | Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   | You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type `setacf -h` and `maxplus2 -h` for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      | If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than `VCC` or `GND` for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   - Exemplar Logic Galileo Extreme-Specific Compiler Settings
   - Synopsys DesignWare-Specific Compiler Settings
   - Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   - Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      | This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   | See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

- JEDEC Files (.jed)
- Programmer Object Files (.pof)
- SRAM Object Files (.sof)
- Hexadecimal (Intel-format) Files (.hex)
- Tabular Text Files (.ttf)

| Refer to the following sources for additional information:

- Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
- Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
- Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware

## Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation

Altera provides the add_dc script, which is availiable in the MAX+PLUS II system directory, to allow you to process MAX+PLUS II-generated Verilog Output Files (.vo) and VHDL Output Files (.vho) to prepare these files for simulation with another EDA tool. The add_dc script runs the add_dclr utility, which inserts a `device_clear` signal that is used for power-up initialization of all registers or flipflops in the design.

The script adds in a top-level signal named `device_clear` and connects it to the `CLRN` pin in all flipflops that should initialize to 0, and to the `PRN` pin of all flipflops that should initialize to 1. If the `CLRN` or `PRN` pin of a flipflop is already being used (i.e., is already connected to a signal), the script modifies the Verilog Output File or VHDL Output File so that the `AND` of the original signal and the `device_clear` pin feed the `CLRN` or `PRN` pin.

To use the add_dc script to process Verilog Output Files and VHDL Output Files before simulation with another EDA tool, follow these steps:

1. Make sure that your design file is located in the current directory, or change to the directory in which the design file is located.

2. Type the following command at the command prompt:

   `\`<path name of add_dc.bat file>`\add_dc` <design name>`` <path name of add_dclr.exe file>

For example, if the both the add_dc.bat and the add_dclr.exe files are located in the d:\maxplus2\exew directory, and the d:\maxplus2\exew directory is specified in the search path, you can type the following command at a command prompt to add a `device_clear` signal to a design named `myfifo` in the file myfifo.vo:

`add_dc myfifo d:\maxplus2\exew`

1. The add_dc script gives a message if the directory contains both a VHDL Output File and a Verilog Output File with the same name (<design name>.vo and <design>.vho). You should delete or rename whichever of those files should not have the `device_clear` signal added. The add_dc script can modify only one design file at a time.

2. When the add_dc script processes the Verilog Output File or VHDL Output File, it creates a backup copy of the original file, with the extension .ori.

3. The add_dc script works only for Verilog Output Files and VHDL Output Files that are generated by MAX+PLUS II.

After you have used the add_dc script and are ready to simulate the resulting Verilog Output File or VHDL Output File with another EDA tool, you should assert the active low `device_clear` pin for a period of time that is long enough for the design to initialize. You can then de-assert the pin, and apply simulation vectors to the design.

## Using Viewlogic SpeedWave VHDL Analyzer & MAX+PLUS II Software

The following topics describe how to use the Viewlogic SpeedWave VHDL Analyzer software with MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment

- Software Requirements
- MAX+PLUS II/Viewlogic Powerview Interface File Organization
- Viewlogic Powerview viewdraw.ini Configuration File
- MAX+PLUS II/Viewlogic Powerview Project File Structure
- Altera-Provided Logic & Symbol Libraries
- The vdpath & mega_lpm Libraries

### VHDL Design Entry

- Design Entry Flow
- Creating VHDL Designs for Use with MAX+PLUS II Software
  - Instantiating the clklock Megafunction in VHDL or Verilog HDL
  - Instantiating RAM & ROM Functions in Viewlogic Powerview Designs
- Entering Resource Assignments
  - Modifying the Assignment & Configuration File with the setacf Utility

### VHDL Analysis

- Analyzing VHDL Files with the SpeedWave VHDL Analyzer Software

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Powerview Command-Line Syntax
- Performing a Functional Simulation with ViewSim Software
- Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
- Performing a Timing Simulation with ViewSim Software
- Compiling Projects with MAX+PLUS II Software
- Programming Altera® Devices

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Viewlogic web site (http://www.Viewlogic.com)

## Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS® II software, you can program an Altera® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

#### Figure 1. MAX+PLUS II Device Programming Flow

| Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

##### Table 1. Altera Programming Hardware

Programming Hardware Option | PCs | UNIX Work- stations | ACEX® 1K Devices | MAX® 3000A Devices | Classic® & MAX 5000 Devices | MAX 7000 & MAX 7000E Devices | MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000
&
MAX 9000A
Devices

FLEX® 6000,
FLEX 6000A,
FLEX 8000,
FLEX 10K,
FLEX 10KA,
FLEX 10KB,
&
FLEX 10KE Devices
In-System
Programming/
Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and
device-specific
adapters
BitBlaster™ Download Cable |  |  |  |  |  |  |  |  |
ByteBlasterMV™ Download Cable |  |  |  |  |  |  |  |  |
MasterBlaster™ Download Cable |  |  |  |  |  |  |  |  |

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

| Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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