## Preparing Files for Timing Verification with PrimeTime Software Using the genpt Utility

After you have compiled a project and generated an EDIF Output File (.edo), Verilog Output File (.vo), or VHDL Output File (.vho) with the MAX+PLUS® II software, you can use Synopsys PrimeTime software to perform timing verification. The Altera-provided genpt utility converts EDIF, Verilog HDL, and VHDL output files for use with Synopsys PrimeTime software.

To prepare MAX+PLUS II-generated EDIF, Verilog HDL, or VHDL output files for timing verification with the Synopsys PrimeTime software, follow these steps:

1. Set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Synopsys Working Environment. Make sure that you have specified the correct path of your local Perl executable, as described in step 4 of that procedure, and that the path in the genpt utility points to that executable.

2. Generate an EDIF Output File (.edo), Verilog Output File (.vo), or VHDL Output File (.vho) and a Standard Delay Format (SDF) Output File (.sdo) by compiling your design with the MAX+PLUS II software, as described in Compiling Projects with MAX+PLUS II Software.

3. Use the genpt utility to convert the EDIF, Verilog HDL, or VHDL output file(s) to PrimeTime-compatible files by typing the following command at the UNIX prompt:

   `genpt (-verilog | -vhdl | -edif)` <design name>`[`<output netlist filename>`]`

   where <design name> is the name of the MAX+PLUS II-generated output file, without the extension. For example, you can type `genpt -vhdl fifo` at the UNIX prompt to convert MAX+PLUS II-generated fifo.vhd and fifo.sdo files into PrimeTime-compatible VHDL and SDF files.

   Based on your settings, the genpt utility generates the following files:

   - A PrimeTime-compatible Verilog HDL file <design name>_pt.v
   - A VHDL file <design name>_pt.vhd or an EDIF netlist file <design name>_pt.edif
   - An SDF file <design name>_pt.sdf.

   If the project contains RAM, ROM, dual-port RAM, or `clklock` functions, the genpt utility generates a <design name>_<type>.db file, where <type> is `ram`, `rom`, `dpram`, or `cklk`, which contains compiled STAMP library cell models for the PrimeTime software. The genpt utility also generates a <design name>_setup.pt PrimeTime setup file, which contains PrimeTime setup commands for compiling generated STAMP models and for reading in the EDIF, Verilog, or VHDL file and the SDF file.

4. Start the PrimeTime software by typing `primetime` at the UNIX prompt. You can also type `pt_shell` at the UNIX prompt to run the PrimeTime software in command-line mode.

5. Source the <design name>_setup.pt PrimeTime setup file. Refer to Synopsys PrimeTime documentation for information on how to perform timing verification with the PrimeTime software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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