## Synplicity-Provided Logic Libraries

Synplicity software provides the altera logic library that is used for synthesizing and compiling VHDL and Verilog HDL designs. The altera library includes the following library files:

Library: | Description:
altera.vhd | A VHDL logic function library that includes the `LCELL`, `SOFT`, `GLOBAL`, `CASCADE`, and `CARRY` primitives for controlling design synthesis and fitting. These primitives can be instantiated directly in your VHDL file. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description.
altera.v | A Verilog HDL logic function library equivalent to the altera.vhd library file.

| You can create your own libraries of custom logic functions for use with Synplicity software. You can use custom logic functions to incorporate an EDIF Input File, Text Design File (.tdf), or any other MAX+PLUS® II-supported design file into a project. The MAX+PLUS II software uses the synplcty.lmf Library Mapping File to map standard Synplicity logic functions to equivalent MAX+PLUS II logic functions. To use custom logic functions, you can create a custom LMF that maps your custom logic functions to the equivalent EDIF Input File, Text Design File (.tdf), or other design file. Go to "Library Mapping File" in MAX+PLUS II Help for more information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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