--
-- Copyright (c) 1996 by Altera Corporation.  All rights reserved.  This text
-- contains proprietary, confidential information of Altera Corporation, and
-- may be used, copied, and/or disclosed only pursuant to the terms of a
-- valid software license agreement with Altera Corporation.  This copyright
-- notice must be retained as part of this text at all times.
--
DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPM7256MC208;
	AUTO_DEVICE = EPM7256GC192;
	AUTO_DEVICE = EPM7192QC160;
	AUTO_DEVICE = EPM7192GC160;
	AUTO_DEVICE = EPM7160QC160;
	AUTO_DEVICE = EPM7160LC84;
	AUTO_DEVICE = EPM7128QC160;
	AUTO_DEVICE = EPM7128QC100;
	AUTO_DEVICE = EPM7128LC84;
	AUTO_DEVICE = EPM7096QC100;
	AUTO_DEVICE = EPM7096LC84;
	AUTO_DEVICE = EPM7096LC68;
	AUTO_DEVICE = EPM7064QC100;
	AUTO_DEVICE = EPM7064LC84;
	AUTO_DEVICE = EPM7064LC68;
	AUTO_DEVICE = EPM7064TC44;
	AUTO_DEVICE = EPM7064LC44;
	AUTO_DEVICE = EPM7032VTC44;
	AUTO_DEVICE = EPM7032VLC44;
	AUTO_DEVICE = EPM7032TC44;
	AUTO_DEVICE = EPM7032QC44;
	AUTO_DEVICE = EPM7032LC44;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	DEVICE_FOR_TIMING_SYNTHESIS = MAX7000;
	MAINTAIN_STABLE_SYNTHESIS = OFF;
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
END;

IGNORED_ASSIGNMENTS
BEGIN
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	MAX7000S_JTAG_USER_CODE = FFFF;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_OE = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	SDOUT = RESERVED_DRIVES_OUT;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	DATA0 = RESERVED_TRI_STATED;
	ENABLE_JTAG = OFF;
	CONFIG_SCHEME = ACTIVE_SERIAL;
	DISABLE_TIME_OUT = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	RELEASE_CLEARS = OFF;
	AUTO_RESTART = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	DEVICE_FAMILY = MAX7000;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	AUTO_REGISTER_PACKING = OFF;
	STYLE = NORMAL;
	AUTO_IO_CELL_REGISTERS = OFF;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_PRESET = ON;
	AUTO_GLOBAL_CLEAR = ON;
	AUTO_GLOBAL_CLOCK = ON;
	MULTI_LEVEL_SYNTHESIS = OFF;
	OPTIMIZE = 5;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	PRESERVE_ALL_NODE_NAME_SYNONYMS = ON;
	FITTER_SETTINGS = NORMAL;
	SMART_RECOMPILE = OFF;
	GENERATE_AHDL_TDO_FILE = OFF;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	OPTIMIZE_TIMING_SNF = OFF;
	TIMING_SNF_EXTRACTOR = ON;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	DESIGN_DOCTOR = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_INPUT_USE_LMF1 = OFF;
	EDIF_OUTPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_INPUT_GND = FALSE;
	EDIF_INPUT_VCC = TRUE;
	EDIF_OUTPUT_EDC_FILE = *.edc;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_INPUT_LMF1 = *.lmf;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_NETLIST_WRITER = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	EDIF_OUTPUT_VERSION = 200;
	EDIF_NETLIST_WRITER = OFF;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;

SIMULATOR_CONFIGURATION
BEGIN
	END_TIME = 0.0ns;
	START_TIME = 0.0ns;
	GLITCH_TIME = 0.0ns;
	GLITCH = OFF;
	OSCILLATION_TIME = 0.0ns;
	OSCILLATION = OFF;
	CHECK_OUTPUTS = OFF;
	SETUP_HOLD = OFF;
	USE_DEVICE = OFF;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	LIST_PATH_FREQUENCY = 10MHz;
	LIST_PATH_COUNT = 10;
	REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
	INCLUDE_PATHS_LESS_THAN = OFF;
	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
	INCLUDE_PATHS_GREATER_THAN = OFF;
	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
	CELL_WIDTH = 18;
	LIST_ONLY_LONGEST_PATH = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	AUTO_RECALCULATE = OFF;
	ANALYSIS_MODE = DELAY_MATRIX;
END;

OTHER_CONFIGURATION
BEGIN
	EXPLICIT_FAMILY = 0;
	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	LCELLS_PER_ROW_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	EXP_PER_LCELL_PERCENT = 100;
	ROW_PINS_PERCENT = 50;
	ORIGINAL_MAXPLUS2_VERSION = 6.0;
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = ON;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = AUTO;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = OFF;
	IO_CELL_REGISTER = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = MANUAL;
END;

