## Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL design that can be synthesized and optimized with Synergy software, follow these steps:

1. You can instantiate the following MAX+PLUS II-provided logic functions in your VHDL design:

   - The alt_mf library contains the Altera® VHDL logic function library, which includes the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` macrofunctions. If you wish to instantiate alt_mf logic functions in your VHDL design, you must first compile this library, as described in Compiling the alt_mf Library.

   - The `clklock` megafunction, which enables the phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the `clklock` Megafunction in VHDL or Verilog HDL for information.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. If you wish to use Standard Delay Format (SDF) Output Files (.sdo) that contain timing information when performing post-compilation timing simulation with Leapfrog software, you must first compile the VITAL library source files, as described in Compiling the alt_vtl Library for for Use with Leapfrog Software.

3. (Optional) To enter resource assignments in your VHDL design, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.

4. After you have completed your VHDL design, synthesize and optimize it with Synergy software, as described in Synthesizing & Optimizing VHDL Files with Synergy Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files, the latter of which includes macrofunction instantiation.

- /usr/maxplus2/examples/cadence/example9/count4.vhd
- /usr/maxplus2/examples/cadence/example10/adder16.vhd

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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