## Instantiating RAM & ROM Functions in Viewlogic Powerview Designs

The MAX+PLUS®II/Viewlogic Powerview interface offers full support for the memory capabilities of the FLEX® 10K device family, including synchronous and asynchronous RAM and ROM, cycle-shared dual-port RAM, dual-port RAM, single-Clock FIFO, and dual-Clock FIFO functions. You can use the Altera-provided genmem utility to generate functional simulation models and timing models for these functions. Type `genmem` at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate. RAM and ROM can be instantiated in both ViewDraw schematics and VHDL designs.

| Refer to Viewlogic documentation for information on simulating projects that contain RAM functions. The procedure for reading an EDIF Output File and preparing it for simulation with ViewSim requires additional steps when the project contains RAM functions.

When you instantiate a RAM or ROM function, follow these general guidelines:

- For ROM functions, you must specify an initial memory content file in the Intel hexadecimal format (.hex) or the Altera® Memory Initialization File (.mif) format. The filename must be the same as the instance name; e.g., the instance name must be unique throughout the whole project, and must contain only valid name characters. The initialization file must reside in the directory containing the project's design files.

- For RAM functions, specifying a memory initialization file is optional.

- For VHDL designs, specify the name of the initial memory content file in the Generic Map Clause of the instance, with the specified type `LPM_FILE`. If you do not use an initial memory content file (e.g., for a RAM function), you should not declare or use the Generic Clause.

- Do not synthesize the genmem-generated VHDL file: it is intended for simulation only.

| The MIF format is supported only for specifying initial memory content when compiling designs within the MAX+PLUS II software. You cannot use a MIF to perform simulation with Viewlogic tools prior to MAX+PLUS II compilation.

To instantiate RAM or ROM in a ViewDraw schematic, follow these steps:

1. Use the genmem utility to generate a memory model by typing the following command at the UNIX prompt:

   `genmem` <memory type>`` <memory size>`-vwlogic`

   For example: `genmem asynrom 256x15 -vwlogic`

2. Start the VHDL-to-symbol utility, vhdl2sym, by double-clicking Button 1 on the max2_vhdl2sym icon in the Altera® Toolbox Design Tools Drawer.

3. Specify the following options in the vhdl2sym dialog box and choose OK to create a symbol. For example, to create the symbol for a 256x15 asynchronous ROM, enter the following settings:

   Option: | Setting:
   --- | ---
   VHDL Source Filename | asyn_rom_256x15.vhd
   Add LEVEL attribute | On

4. Choose Comp (Add menu), type <design name> in the Enter Name box, and choose OK.

To instantiate a RAM or ROM function in VHDL, follow these steps:

1. Repeat step 1 above.
2. Create a VHDL design that incorporates the text from the genmem-generated Component Declaration, <memory name>.cmp, and instantiate the <memory name> function.

Figure 1 shows a VHDL design that instantiates asyn_rom_256x15.vhd, a 256 x 15 ROM function.

Figure 1. VHDL Design File with ROM Instantiation (tstrom.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    ENTITY tstrom IS
            PORT (
              addr    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
              memenab : IN STD_LOGIC;
              q       : OUT STD_LOGIC_VECTOR (14 DOWNTO 0));
    END tstrom;
    ARCHITECTURE behavior OF tstrom IS

    COMPONENT asyn_rom_256x15
         GENERIC (LPM_FILE : string);
         PORT (Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               MemEnab : IN STD_LOGIC;
               Q       : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
         );
    END COMPONENT;
    BEGIN

       u1: asyn_rom_256x15
            GENERIC MAP (LPM_FILE => "u1.hex")
       PORT MAP (Address => addr, MemEnab => memenab, Q =>q);
    END behavior;

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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