## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software

After you have created a VHDL or Verilog HDL design, you can use Exemplar Logic's Leonardo software to synthesize and optimize your VHDL Design File (.vhd) or Verilog Design File (.v) and prepare it for compilation with the MAX+PLUS® II Compiler.

To synthesize and optimize your project and generate an EDIF netlist file with Leonardo software, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software.

4. Select the icon for your project's design file from the Navigator window, press Button 3, and choose max2_leonardo to start the Leonardo software and open the Exemplar Logic Leonardo window. You can also start Leonardo by typing `max2_leonardo` at the UNIX prompt.

5. Click Button 1 on the Flow Guide toolbar button to open the Customize Flow Guide dialog box.

6. Turn on the Altera EDIF Output File checkbox under Output Flow.

7. Choose Run Flow Guide to open the Flow Guide window and specify the appropriate options in the following modules to synthesize your project:

1. Choose Load Library to open the Load Library dialog box. If necessary, select FPGA Enhanced from the Tech Type drop-down list box. Select the target Altera® device family from the list of supported device families and choose Load to close the dialog box.

2. Choose Read to open the Read dialog box. Turn on VHDL or Verilog HDL under Format, ensure that the appropriate library name appears under Work Library, and type the name of your design file in the Filename box or select it from the Select a File dialog box. Choose Read to close the dialog box.

3. Choose Pre-Optimize to open the Pre-Optimize dialog box. Choose Pre-Optimize to accept the default pre-optimization settings and close the dialog box.

4. Choose Optimize to open the Optimize dialog box. Choose Optimize to accept the default optimization settings and close the dialog box.

5. Choose Write Altera to open the Convenience Procedures dialog box. Type `write_altera` in the Procedure box or select write_altera from the list box and choose Run to automatically generate <design name>.edf.

8. Choose Exit Flow Guide to return to the Leonardo window.

9. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL Design Files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software in these MAX+PLUS II ACCESSSM Key topics for related information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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