## Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL design that can be synthesized and optimized with ViewSynthesis software, follow these steps:

1. You can instantiate the following Altera-provided logic functions in your VHDL design:

   - The alt_mf library contains the Altera® VHDL logic function library, which includes MAX+PLUS II-specific primitives and the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` macrofunctions. If you wish to instantiate alt_mf logic functions in your VHDL design, you must first analyze all functions in the alt_mf/src directory. See Analyzing VHDL Files with the Vantage VHDL Analyzer Software for details.

   - The `clklock` megafunction, which enables the phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for information.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. (Optional) To enter resource assignments in your VHDL design, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.

Once you have created a VHDL design, you can analyze it, synthesize it, and generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:

- You can analyze, functionally simulate, and synthesize the VHDL design, then generate an EDIF netlist file by following the steps in these topics:

  - Analyzing VHDL Files with the Vantage VHDL Analyzer Software
  - Performing a Functional Simulation with ViewSim Software
  - Synthesizing & Optimizing VHDL Designs with ViewSynthesis Software
  - Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility

- You can use the VHDL <-> max2 utility in the Max2 Express Drawer to automatically analyze and synthesize the VHDL design, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and create a .vsm file for simulation. See Using the Max2 Express Drawer's VHDL <-> max2 Utility in these MAX+PLUS II ACCESSSM Key topics for details.

Installing the Altera-provided MAX+PLUS II/Viewlogic Powerview interface on your computer automatically creates the following sample VHDL files:

- /usr/maxplus2/examples/Viewlogic/example5/count4.vhd
- /usr/maxplus2/examples/Viewlogic/example5/count8.vhd

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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