## DesignWare FLEX 8000 Synthesis Example

Figure 1 shows a sample VHDL design, design_one.vhd, which illustrates component inference with the DesignWare interface for FLEX® 8000 devices.

Figure 1. VHDL Design File (design_one.vhd)
This design illustrates the sum of A + B.
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.ALL;
    ENTITY design_one IS
       PORT (a,b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
             f   : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
    END design_one;
    ARCHITECTURE add_design OF design_one IS
    BEGIN
     f <= a + b;
    END add_design;

When the VHDL Compiler or the HDL Compiler for Verilog software analyzes and elaborates the design, it replaces the "+" operator with its synthetic operator equivalent.

Figure 2 shows the design as it appears in the Design Analyzer software after it has been analyzed and elaborated by the VHDL Compiler software.

Figure 2. design_one.vhd after Analysis & Elaboration

When you synthesize a design, the Design Compiler or FPGA Compiler software uses the synthetic library to match the synthetic operator to the FLEX-optimized logical implementation in the technology library. The Synopsys Design Compiler or FPGA Compiler software then instantiates and interconnects the correct number of `flex_add` and `flex_carry` functions to produce the 8-bit adder shown in Figure 1. When you save a compiled design as a VHDL, Verilog HDL or EDIF file, the file preserves the number of `flex_add` and `flex_carry` functions, as well as their interconnections. Consequently, area and performance predictions that you make in the Synopsys design environment closely match the final MAX+PLUS® II result.

Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries.

Table 2. FLEX 6000, FLEX 8000, and FLEX 10K Synthetic Library Functions
Name | Function
--- | ---
`flex_add` | Sum of A, B, and Carry-In
`flex_carry` | Carry of A, B, and Carry-In
`flex_sub` | Difference of A, B, and Borrow-In
`flex_borrow` | Borrow of A, B, and Borrow-In
`flex_gt,` `flex_sgt` | Greater than (`flex_gt` is unsigned; `flex_sgt` is signed)
`flex_carry_gt` | Greater than Carry
`flex_lt,` `flex_slt` | Less than (`flex_lt` is unsigned; `flex_slt` is signed)
`flex_carry_lt` | Less than Carry
`flex_gteq,``flex_sgteq` | Greater than or equal to (`flex_gteq` is unsigned; `flex_sgteq` is signed)
`flex_carry_gteq` | Greater than or equal to Carry
`flex_inc` | Incrementer (Count = Count + 1)
`flex_carry_inc` | Incrementer Carry (Count = Count + 1)
`flex_dec` | Decrementer (Count = Count - 1)
`flex_carry_dec` | Decrementer Carry (Count = Count - 1)
`flex_lteq, flex_slteq` | Less than or equal to (`flex_lteq` is unsigned; `flex_slteq` is signed)
`flex_carry_lteq` | Less than or equal to Carry
`flex_count` | Counter
`aflex_carry_count` | Counter Carry
`flex_add_sub` | Adder/Subtractor
`flex_inc_dec` | Incrementer/Decrementer
`flex_umult, flex_smult` | Multiplier (`flex_umult` is unsigned; `flex_smult` is signed)

Figure 3 shows design_one.vhd after it has been synthesized with the Design Compiler.

Figure 3. design_one.vhd Synthesized & Resolved for FLEX 6000, FLEX 8000 & FLEX 10K Architecture

After you save the design as an EDIF Input File (.edf) and process it with the MAX+PLUS II Compiler, the Compiler replaces instances of `flex_add` and `flex_carry` with FLEX-optimized versions, as shown in Figure 4. The MAX+PLUS II Compiler maps these functions into a single logic element (LE). The result is a high-speed 8-bit adder that fits into 8 LEs.

Figure 4. One Slice of the design_one 8-bit Adder Design with Optimized FLEX 8000 Functions

| Refer to the following sources for related information on DesignWare and the Synopsys VHDL Compiler:

- Synopsys DesignWare Databook
- VHDL Compiler Reference Manual

| Go to FLEX Devices, which is available on the web, for additional information:

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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