## Specifying Speed/Area & CPU Effort Settings with the FPGA Express Software

FPGA Express software allows you to choose either speed or area options and to specify either high or low CPU effort in logic optimization. Optimization goals are set on a global basis or on particular levels of hierarchy.

To set global optimization controls in the FPGA Express software, follow these steps:

1. If you have not already done so, identify the top-level design for your project in the Design Sources window. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.

2. Select either speed or area under Optimize for to specify the optimization goal for the entire design:

   - Selecting the speed option minimizes delay by synthesizing circuits to contain the least number of levels of combinatorial logic, sometimes yielding increased design area. This setting maximizes operating frequency and minimizes combinatorial path delays.

   - Selecting the area option minimizes the combinatorial logic resources used, sometimes yielding reduced speed. This setting minimizes combinatorial logic usage. Altera also recommends selecting the WYSIWYG synthesis style when optimizing for area, as described in Specifying the MAX+PLUS II Logic Synthesis Style with FPGA Express Software.

3. Select either high or low under Effort to specify the CPU effort level:

   - Selecting the low option increases compilation speed at the expense of larger combinatorial area. This option is most useful for minimizing compilation time for very large designs when neither speed nor area are critical.

   - Selecting the high option decreases the combinatorial area at the expense of compilation speed. This option is recommended in speed- or area-critical designs.

You can set the same optimization controls on individual levels of hierarchy for greater control. This strategy is useful when your design contains hierarchical blocks with different requirements. For example, some blocks may be time-critical while others are not. To obtain the best resuls, you should optimize time-critical blocks for speed and other blocks for area.

To set optimization goals on a particular level of hierarchy, follow these steps:

1. Select the pre-optimized chip icon in the Chips window, press Button 2 and choose Edit Constraints to display the constraints tables.
2. Select the Modules tab.
3. Find the row that displays the level of hierarchy for which you want to set an optimization goal.
4. In the Optimize for column of that row, click inside the cell and select either speed or area from the options that appear.
5. In the Effort column of that row, click inside the cell and select either high or low from the available options.

6. If you have not already done so, assign a device and Clock frequency, as described in Assigning a Device & Clock Frequency (fMAX).

7. Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

| Optimization settings are the same for an entire design file, regardless of its level of hierarchy.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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