## Analyzing VHDL or Verilog HDL Designs with the Synplify HDL Analyst

You can use the optional Synplify HDL Analyst to analyze and evaluate the performance of your design graphically. The Synplify HDL Analyst instantly generates Register Transfer Level (RTL) schematics, as well as technology-mapped, gate-level schematics. You can instantly identify and fix potential problems earlier in the design cycle by cross-probing between the RTL schematics, gate-level schematics, and HDL source code. The Synplify HDL Analyst also highlights critical paths within the design to show which signals require optimization for performance. After you determine the critical speed paths, you can add timing constraints either to the VHDL or Verilog HDL source file or to a separate Synplify Design Constraints File (.sdc) to improve design performance.

To use the Synplify HDL Analyst after synthesizing your design with Synplify software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS® II/Synplicity Working Environment.

2. Create a VHDL or Verilog HDL design and save it in your working directory, as described in Creating VHDL Designs for Use with MAX+PLUS II Software or Creating Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Synthesize and optimize your VHDL or Verilog HDL design with Synplify software, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

4. Choose an HDL Analyst view:

   | Choose RTL View (HDL_Analyst menu) to view the RTL schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (`+`) symbol.

   or:

   | Choose Technology View (HDL_Analyst menu) to view the gate-level schematic. When you select this view, the HDL Analyst displays a graphical representation of the design and the mouse pointer becomes a plus (`+`) symbol.

5. In either the RTL or Technology View, perform one or more of the following actions:

   - Double-click the plus (`+`) symbol pointer on a port name or symbol to cross-probe your VHDL or Verilog HDL source design files.

     | Because Synplify combines the `a + b` and `a - b` operations, cross-probing will highlight the Case Statement that defines both functions.

   - Choose Find (HDL_Analyst menu) to select specific signals quickly in your design.

   - Choose Show Critical Path (HDL_Analyst menu) to highlight the critical paths in the design.

   - Select Filter Schematic (HDL_Analyst menu) to show only the nodes you have selected.

6. If necessary, correct the design and repeat the steps described in Synthesizing & Optimizing VHDL or Verilog HDL Files with Synplify Software.

7. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Synplify Topics | Documentation Conventions Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.