## Performing a Timing Simulation with Fusion/VCS for Powerview Software

After you have compiled a project with the MAX+PLUS® II software to generate a VHDL Output File (.vho) and a Standard Delay Format (SDF) Output File (.sdo), you can perform a timing simulation with Fusion/VCS software.

To simulate a project with Fusion/VCS software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Generate a VHDL Output File (.vdo) and an SDF ver 2.1 or 1.0 Output File (.sdo) for your project, as described in Compiling Projects with MAX+PLUS II Software.

3. Create a new sim directory under your max2 directory to contain your Fusion/VCS simulation-related files.

4. To use the SDF Output File with the Fusion/VCS software, create a PLI table file (.tab) in the <project name>/max2/sim directory that contains the following line:

   `$sdf_annotate call=sdf_annotate_call acc=tchk, mp:`<project name>

5. Open the Fusion/VCS dialog box by choosing the max2_VCS button from the Altera® Design Tools Drawer in the Powerview Cockpit.

   1. Type <project name>`/max2/`<project name>`.vo` in the Verilog Design and Object Files box.

   2. Type <project name>`.tab` in the PLI Table File box.

   3. Type <project name>`/max2/alt_max2.vo` in the Verilog Library File 1 box.

   4. (Optional) To use a command file or to set stimuli during simulation, select the Debug option in the VCS box and type the name of the command file in the Simulation Command-file box.

      | When using a command file or setting stimuli, include the signal scope as part of the signal name. For example, to manipulate clk, a top-level signal in the fadd project, name the signal as `fadd.clk`.

   5. Choose OK.

| Go to Performing a Timing Simulation with ViewSim Software in these MAX+PLUS II ACCESSSM Key topics for related information:

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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