## Using the Altera VHDL Express (vhd_exprss) Utility

Once you have created a VHDL Design File (.vhd) for your project, you can use the Altera® VHDL Express (vhd_exprss) utility to synthesize and optimize the design and generate an EDIF netlist file with Galileo Extreme software; process the EDIF netlist file with the MAX+PLUS II software to generate a VHDL Output File (.vho); and prepare the VHDL Output File for simulation with QuickHDL software. The vhd_exprss utility creates all necessary subdirectories and copies all files to the correct locations.

To use the vhd_exprss utility, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL Design File that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Select the VHDL Design File for your project, press Button 3, and choose Open vhd_exprss from the Navigator window to start the Altera VHDL Express tool.

4. Specify settings for the Input HDL File, Altera Device Family, Max2 Synthesis Style, Process Direction, and Verbose options, and the Optimize and Effort runtime options, in the vhd_exprss dialog box, and choose OK.

5. If necessary, correct any errors in the VHDL Design File and recompile the project. The vhd_exprss utility generates a VHDL output file in the appropriate directory.

6. Simulate your project, as described in Performing a Timing Simulation with QuickHDL Software.

| Go to Performing a Timing Analysis with QuickPath Software in these MAX+PLUS II ACCESSSM Key topics for related information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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