## Performing a Functional Simulation with QuickHDL Pro Software

You can use Mentor Graphics QuickHDL Pro software to functionally simulate mixed-level schematic and VHDL designs before compiling them with the MAX+PLUS® II Compiler.

Refer to Mentor Graphics Getting Started with QuickHDL Pro page 2-1 and 3-1 for compatible design configurations.

To functionally simulate a QuickHDL at Top Level design, follow the steps in Getting Started with QuickHDL Pro, Chapter 2.

To functionally simulate a QuickSim II at Top Level design, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
2. Create a schematic design using QuickHDL models. Refer to Creating Design Architect Schematics for Use with MAX+PLUS II Software.
3. Compile the QuickHDL model using the QuickHDL Compiler with the -qhpro_syminfo option. (This is done automatically for LPM functions if you choose to compile the LPM models when saving the schematic.)
4. Start Design Architect by double-clicking Button 1 on the max_da icon in the Design Manager tools window.
5. Choose Open from the File menu, then choose Sheet from the Open menu to open the top level schematic.
6. Select the symbol for the VHDL model and choose Begin Edit Symbol from the Edit menu.
7. Press Button 3 to display the the Design Architect pop-up menu. Choose Add Menu from the Other Menus menu, then choose Set VHDL Info. Choose Import from Entity to display the "Import Entity Info" dialog box.
8. Specify the following options in the "Import Entity Info" dialog box:

   1. QHDL InitFile: Specify your quickhdl.ini file.

   2. Library Logical Name: Click on Choose Library button and fill the "Choose VHDL Library" form with your work library.

   3. Entity Name: Click on Choose Entity button and select the name of your entity.

   4. Default Architecture: Click on Choose Arch button and select corresponding architecture for the entity.

   After filling in the above information, click on OK to close the form.

9. Check the symbol with defaults. If there are no errors, save the symbol with default registration by choosing Save Symbol from the File menu, then choose Default Registration.
10. Choose End Edit Symbol from the Edit menu to close the Symbol Editor session. In the schematic window, select the symbol you have just edited and choose Object from the Report menu, then choose All from the Selected menu. In the report transcript, make sure the MODEL property is set to qhpro to ensure that the model will work with QuickHDL Pro.
11. Select the folder for your project, press button 3, and choose Open max2_qvpro to start QuickHDL Pro. You can also start QuickHDL Pro by typing max2_qvpro at the UNIX prompt. In the QVHDL Pro System dialog box, make sure EDDM Design is selected for Invoke on and the correct path name is specified for the design. Choose OK to start the QuickHDL Pro. A QHPro (QuickSim II) window and a QHPro (QuickHDL) window appear on the screen.
12. Use the QuickSim II window to simulate the top level schematic and the QuickHDL window to simulate the VHDL portion of the design.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Instantiating LPM Functions in Design Architect Schematics
- Performing a Functional Simulation with QuickHDL Software

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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