## Using Mentor Graphics & Exemplar Logic Tools with MAX+PLUS II Software

The following topics describe how to use a variety of Mentor Graphics and Exemplar Logic tools as part of a complete design flow that includes the MAX+PLUS® II software. If you use only one Mentor Graphics or Exemplar Logic tool, click List by Tool and select the tool name to view the list of topics only for that tool. Click on one of the following topics for information:

CLICK HERE to open a printable version of all topics listed on this page.

### Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

- Software Requirements
- Altera-Provided Logic & Symbol Libraries
- Local Work Area Directory Structure
- Mentor Graphics Project Directory Structure
- MAX+PLUS II Project Directory Structure
- MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

### Design Flow For All Mentor Graphics/Exemplar Logic Tools

### Design Entry

- #### Design Entry Flow

- #### Design Architect

- Creating Design Architect Schematics for Use with MAX+PLUS II Software

- Instantiating the clklock Megafunction in Design Architect Schematics
- Instantiating LPM Functions in Design Architect Schematics

- Entering Resource Assignments

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility
- BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols

- Creating Hierarchical Projects with Design Architect Software
- Performing a Functional Simulation with DVE & QuickSim II Software
- Performing a Functional Simulation with QuickHDL Pro Software
- Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility

- #### VHDL & Verilog HDL

- Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software

- Instantiating the clklock Megafunction in VHDL or Verilog HDL
- Instantiating LPM Functions in VHDL

- Entering Resource Assignments

- Modifying the Assignment & Configuration File with the setacf Utility

- Performing a Functional Simulation with QuickHDL Software
- Performing a Functional Simulation with QuickHDL Pro Software
- Creating Hierarchical Projects with Design Architect Software

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software
- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software

### Compilation

- Project Compilation Flow
- Compiling Projects with MAX+PLUS II Software

- Exemplar Logic Galileo ExtremeSpecific Compiler Settings

- Using the Altera Schematic Express (sch_exprss) Utility
- Using the Altera VHDL Express (vhd_exprss) Utility

### BackAnnotation

- BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols

### Simulation/Timing Analysis

- Project Simulation/Timing Analysis Flow
- Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
- Performing a Timing Simulation with DVE & QuickSim II Software
- Performing a Timing Simulation with QuickHDL Software
- Performing a Timing Analysis with QuickPath Software

### Device Programming

- Programming Altera Devices

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Mentor Graphics web site (http://www.mentor.com)

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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