## Creating ViewDraw Schematics for Use with MAX+PLUS II Software

You can create ViewDraw schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II software.

To create a ViewDraw schematic for use with the MAX+PLUS II software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Start Powerview by typing `powerview` at a UNIX prompt.

3. In the Cockpit window, select Altera in the Current ToolBox drop-down list box, and select the drawer you want to use, i.e., Design Tools or Max2 Express, in the Current Drawer drop-down list box.

4. Choose Create (Project menu) from your working directory to create your project directory. Choose OK.

5. Choose SearchOrder (Project menu) to add the appropriate library directories and aliases to your viewdraw.ini file in the appropriate search order. Refer to Viewlogic Powerview viewdraw.ini Configuration File for more information on Powerview application libraries.

6. Start ViewDraw by double-clicking Button 1 on the max2_VDraw icon in the drawer that you selected in step 3, type the name of the schematic, and choose OK. You can also start the ViewDraw software by typing `viewdraw` at the UNIX prompt.

7. Choose Comp (Add menu) to add components to the schematic. You can use functions from the alt_max2, builtin, and 74ls libraries. For information on Altera-provided libraries, go to Altera-Provided Logic & Symbol Libraries.

   Instructions for instantiating specific functions are provided in the following MAX+PLUS II ACCESSSM Key topics:

   - Instantiating LPM Functions in ViewDraw Schematics
   - Instantiating RAM & ROM Functions in Viewlogic Powerview Designs

   | You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPPSM). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

8. If you instantiate a `clklock` megafunction, choose the Dialog command (Attr menu), then choose the All command (Dialog menu) to specify the values of the `INPUT_FREQUENCY` and `CLOCKBOOST` parameters. For detailed information on the `clklock` megafunction, choose Megafunctions/LPM from the MAX+PLUS II Help menu.

9. If you wish to create a hierarchical design that contains symbols representing other design files, such as Altera® Hardware Description Language (AHDL) Text Design Files (.tdf), go to Creating Hierarchical Projects in ViewDraw Schematics.

10. Choose Net (Add menu) to add nets to the schematic.

11. Choose Bus (Add menu) to add buses to the schematic.

12. Choose Label (Add menu) to attach labels to nets and buses. When you are naming and labeling buses, make sure you use the format <bus name>[<most significant bit>:<least significant bit>], and that you label both the net and the pin.

13. (Optional) To enter resource assignments in your schematic, select a symbol or a net that feeds an output and use the Attr command (Add menu) to add the assignments. For more information, go to Entering Resource Assignments. You can also enter resource assignments from the MAX+PLUS II software.

14. Choose Write (File menu) to check and save both the schematic with the name .sch/<design name>.1 and the wirelist with the name ./wir/<design name>.1.

15. (Optional) Perform a functional simulation, as described in Performing a Functional Simulation with ViewSim Software.

16. Once you have created a schematic, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:

    - You can create an EDIF netlist file, as described in Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility You must use this method if your ViewDraw schematic instantiates Library of Parameterized Modules (LPM) functions.
    - You can use the SCH <-> max2 utility in the Max2 Express drawer to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and generate a .vsm file for simulation, as described in Using the Max2 Express Drawer's SCH <-> max2 Utility.

Installing the Altera-provided MAX+PLUS II/Viewlogic interface on your computer automatically creates the following sample ViewDraw schematic files:

- /usr/maxplus2/examples/viewlogic/example1/fadd
- /usr/maxplus2/examples/viewlogic/example3/fadd2
- /usr/maxplus2/examples/viewlogic/example4/fadd2mpp
- /usr/maxplus2/examples/viewlogic/example7/fifo

| Go to Powerview Command-Line Syntax in these MAX+PLUS II ACCESS Key topics for related information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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