// MAX+plus II Verilog Example
// Combinatorial Always Statement 
// Copyright (c) 1994 Altera Corporation

module proc (d, q);

    input  [2:0] d;
    output [1:0] q;

    integer num_bits;

    always @(d)
    begin: block
        integer i;

        num_bits = 0;
        for (i = 0; i < 3; i = i + 1)
           if (d[i] == 1)
               num_bits = num_bits + 1;
    end

    assign q = num_bits;

endmodule

