## Performing a Functional Simulation with ViewSim Software

You can use Viewlogic ViewSim software to perform a functional simulation of a ViewDraw schematic or a VHDL Design File (.vhd) before compiling your project with the MAX+PLUS II Compiler. Follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Create a ViewDraw schematic that follows the guidelines in Creating ViewDraw Schematics for Use with MAX+PLUS II Software. Then go to step 3.

   or:

   Create a VHDL Design File <design name>.vhd and analyze it, as described in the following MAX+PLUS II ACCESSSM Key topics:

   - Creating VHDL Designs for Use with MAX+PLUS II Software
   - Analyzing VHDL Files with the Vantage VHDL Analyzer Software

   Then go to step 7.

3. With the schematic open in the ViewDraw editor, add `CLR` and `PRE` inputs to any flipflops in your design, or tie the `CLR` and `PRE` ports of the flipflops to VCC. (Use the `PWR` primitive from the builtin library.)

4. Choose Write To (File menu) and save the schematic as <design name>_funct.

5. Start the vsm utility by double-clicking Button 1 on the max2_vsmnet icon in the Altera® Toolbox Design Tools Drawer.

6. Specify the following options in the vsm dialog box and choose OK to generate the <design name>_funct.vsm file:

   Option: | Setting: |
   Design Name | <design name>_funct |
   Level |  | (blank)

7. Create a simulation command file (.cmd) for simulation with ViewSim software. Alternatively, you can enter commands at the prompt in the ViewSim window. Refer to your Viewlogic documentation for more information on creating ViewSim command files.

8. Start the ViewSim simulation tool by double-clicking Button 1 on the max2_VSim icon in the Design Tools Drawer.

9. If you wish to simulate a ViewDraw schematic, specify the following options in the ViewSim dialog box, then go to step 11.

   Option: | Setting:
   Design Name | <design name>_funct
   Command File | <design name>_funct.cmd
   VHDL Source Window | OFF
   VHDL Debugging | OFF

10. If you wish to simulate a VHDL design, specify the following options in the ViewSim dialog box:

    Option: | Setting:
    Design Name | <design name>
    Command File | <design name>.cmd
    Graphical Interface | ON
    VHDL Source Window | OFF or ON
    VHDL Debugging | OFF or ON

11. Choose OK to simulate the design. ViewSim software simulates the design and starts the ViewTrace waveform editor to allow you to observe the simulation results.

12. Use the edifneto utility to generate an EDIF Netlist File (.edf) that can be imported into the MAX+PLUS II software, as described in Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility.

| Go to ViewSim documentation for complete details on simulating a project and using ViewTrace to observe waveform output results.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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