## Using Viewlogic Powerview Tools with MAX+PLUS II Software

The following topics describe how to use Viewlogic Powerview tools as part of a complete design flow that includes the MAX+PLUS® II software. If you use only one Viewlogic Powerview tool, click List by Tool and select the tool name to view the list of topics only for that tool. Click on one of the following topics for information:

CLICK HERE to open a printable version of all topics listed on this page.

### Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment

- Software Requirements
- MAX+PLUS II/Viewlogic Powerview Interface File Organization
- Viewlogic Powerview viewdraw.ini Configuration File
- Viewlogic Powerview Graphical User Interface & the Altera Toolbox
- MAX+PLUS II/Viewlogic Powerview Project File Structure
- Altera-Provided Logic & Symbol Libraries
- The vdpath & mega_lpm Libraries

### Design Flow for All Viewlogic Powerview Tools

### Design Entry

- Design Entry Flow

- ViewDraw
  - Creating ViewDraw Schematics for Use with MAX+PLUS II Software
    - Instantiating LPM Functions in ViewDraw Schematics
    - Instantiating RAM & ROM Functions in Viewlogic Powerview Designs
  - Creating Hierarchical Projects in ViewDraw Schematics
  - Entering Resource Assignments
    - Assigning Pins, Logic Cells & Chips
    - Assigning Cliques
    - Assigning Logic Options
    - Modifying the Assignment & Configuration File with the setacf Utility
  - Performing a Functional Simulation with ViewSim Software
  - Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility

- VHDL
  - Creating VHDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
    - Instantiating RAM & ROM Functions in Viewlogic Powerview Designs
  - Entering Resource Assignments
    - Modifying the Assignment & Configuration File with the setacf Utility
  - Analyzing VHDL Files with the Vantage VHDL Analyzer Software
  - Performing a Functional Simulation with ViewSim Software
  - Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL Designs with ViewSynthesis Software

### Compilation

- Project Compilation Flow
- Compiling Projects with MAX+PLUS II Software
- Using the Max2 Express Drawer's SCH <-> max2 Utility
- Using the Max2 Express Drawer's VHDL <-> max2 Utility

### Simulation

- Project Simulation Flow

- ViewSim
  - Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
  - Analyzing VHDL Files with the Vantage VHDL Analyzer Software
  - Performing a Functional Simulation with ViewSim Software
  - Performing a Timing Simulation with ViewSim Software
    - Using ViewDraw & ViewGen Software to Prepare for Multi-Device Board-Level Simulation with ViewSim Software

- Fusion/VCS
  - Performing a Timing Simulation with Fusion/VCS for Powerview Software

### Timing Verification

- Timing Verification Flow
- Performing Timing Verification of EDIF Output Files (.edo) with MOTIVE & MOTIVE for Powerview Software
- Performing Timing Verification of Verilog Output Files (.vo) with MOTIVE Software

### Device Programming

- Programming Altera® Devices

| Go to Powerview Command-Line Syntax in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Viewlogic web site (http://www.Viewlogic.com)

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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