## Altera DesignWare FLEX 6000, FLEX 8000 & FLEX 10K Synthetic Libraries

The Altera® DesignWare interface for the FLEX® 6000, FLEX 8000, and FLEX 10K device families provides accurate area and timing prediction for designs that have been synthesized by the Synopsys design tools and targeted for FLEX devices. Altera's DesignWare interface also ensures that the area and timing information closely matches the final FLEX device implementation generated by the MAX+PLUS® II Compiler. The DesignWare interface synthesizes FLEX 6000, FLEX 8000 and FLEX 10K designs by operator inference. This interface supports bus widths of up to 32 bits, except adder functions, which support bus widths of up to 64 bits.

The Altera DesignWare interface for FLEX devices offers three major advantages to Synopsys designers:

- Automatic access to FLEX carry and cascade chain functions
- Optimal routing of FLEX designs
- Improved area and performance prediction capability in Synopsys tools

Table 1 lists the Altera DesignWare synthetic libraries for FLEX 6000, FLEX 8000, and FLEX 10K devices.

Table 1. FLEX 6000, FLEX 8000 & FLEX 10K DesignWare Synthetic Libraries
Altera Device Family | Synopsys Design Compiler | Synopsys FPGA Compiler
--- | --- | ---
FLEX 6000 Synthetic Library | flex6000-2.sldb flex6000-3.sldb | flex6000-2_fpga.sldb flex6000-3_fpga.sldb
FLEX 8000 Synthetic Library | flex8000.sldb flex8000-2.sldb flex8000-3.sldb flex8000-4.sldb flex8000-5.sldb
flex8000-6.sldb
flex8000_fpga.sldb
flex8000-2_fpga.sldb
flex8000-3_fpga.sldb
flex8000-4_fpga.sldb
flex8000-5_fpga.sldb
flex8000-6_fpga.sldb
FLEX 10K Synthetic Library | flex10k.sldb flex10k-2.sldb flex10k-3.sldb flex10k-4.sldb flex10k-5.sldb | flex10k_fpga.sldb flex10k-2_fpga.sldb flex10k-3_fpga.sldb flex10k-4_fpga.sldb flex10k-5_fpga.sldb

Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries. Refer to DesignWare FLEX 8000 Synthesis Example for an example showing how DesignWare synthesis affects design processing.

Table 2. FLEX 6000, FLEX 8000, and FLEX 10K Synthetic Library Functions
Name | Function
--- | ---
`flex_add` | Sum of A, B, and Carry-In
`flex_carry` | Carry of A, B, and Carry-In
`flex_sub` | Difference of A, B, and Borrow-In
`flex_borrow` | Borrow of A, B, and Borrow-In
`flex_gt,` `flex_sgt` | Greater than (`flex_gt` is unsigned; `flex_sgt` is signed)
`flex_carry_gt` | Greater than Carry
`flex_lt,` `flex_slt` | Less than (`flex_lt` is unsigned; `flex_slt` is signed)
`flex_carry_lt` | Less than Carry
`flex_gteq,``flex_sgteq` | Greater than or equal to (`flex_gteq` is unsigned; `flex_sgteq` is signed)
`flex_carry_gteq` | Greater than or equal to Carry
`flex_inc` | Incrementer (Count = Count + 1)
`flex_carry_inc` | Incrementer Carry (Count = Count + 1)
`flex_dec` | Decrementer (Count = Count - 1)
`flex_carry_dec` | Decrementer Carry (Count = Count - 1)
`flex_lteq, flex_slteq` | Less than or equal to (`flex_lteq` is unsigned; `flex_slteq` is signed)
`flex_carry_lteq` | Less than or equal to Carry
`flex_count` | Counter
`aflex_carry_count` | Counter Carry
`flex_add_sub` | Adder/Subtractor
`flex_inc_dec` | Incrementer/Decrementer
`flex_umult, flex_smult` | Multiplier (`flex_umult` is unsigned; `flex_smult` is signed)

| Go to the following sources for related information:

- Setting Up the DesignWare Interface in these MAX+PLUS II ACCESSSM Key topics
- Synopsys DesignWare Databook
- VHDL Compiler Reference Manual

| Go to the following topics, which are available on the web, for additional information:

- FLEX 6000 Device Family
- FLEX 8000 Device Family
- FLEX 10K Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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