## Performing a Pre-Routing or Functional Simulation with VSS Software

After you have synthesized and optimized a VHDL or Verilog HDL design with the Design Compiler or FPGA Compiler software, you can perform a pre-routing or functional simulation with the Synopsys VHDL System Simulator (VSS) software.

To perform a pre-routing/functional simulation, follow these steps:

1. Be sure to set up the working environment correctly, as described in the following topics:
   - Setting Up the MAX+PLUS II/Synopsys Working Environment
   - Setting Up Design Compiler & FPGA Compiler Configuration Files
   - Setting Up the DesignWare Interface
   - Setting Up VSS Configuration Files

2. Create a VHDL or Verilog HDL design file that follows the guidelines described in one of the following topics:
   - Creating VHDL Designs for Use with MAX+PLUS II Software
   - Creating Verilog HDL Designs for Use with MAX+PLUS II Software

3. Synthesize and optimize your design with the Design Compiler or FPGA Compiler, as described in Synthesizing & Optimizing VHDL & Verilog HDL Files with Design Compiler or FPGA Compiler Software.
4. Save your design as a VHDL Design File (.vhd).

   | VSS requires each architecture/entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis.

5. Use VSS and one of the Altera pre-routing functional simulation libraries to simulate the design.

6. When you are ready to compile your project with MAX+PLUS II software, save the design as an EDIF netlist file (.edf), then process it as described in Compiling Projects with MAX+PLUS II Software.

| Refer to the following sources for related information:

- VHDL System Simulator Core Programs Manual for more information about VSS
- Performing a Timing Simulation with VSS Software

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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