## Using the Max2 Express Drawer's VHDL <-> max2 Utility

Once you have created a VHDL Design File (.vhd) for your project, you can use the VHDL <-> max2 utility in the Max2 Express drawer to synthesize and optimize the design; generate an EDIF netlist file; and process the EDIF netlist file with the MAX+PLUS II Compiler to generate an EDIF Output File (.edo) for simulation. The VHDL <-> max2 utility creates all necessary subdirectories and copies all files to the correct locations.

To use the VHDL <-> max2 utility, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Create a VHDL Design File that follows the guidelines described in Creating VHDL Designs for Use with MAX+PLUS II Software.

3. Start the VHDL <-> max2 utility by double-clicking Button 1 on the VHDL <-> max2 icon in the Max2 Express Drawer.

4. Specify the Input VHDL file, Viewlogic Optimize Style, Viewlogic Timing Constraint File, Altera Device Family, Max2 Synthesis Style, and the Process Direction options in the VHDL <-> max2 dialog box and choose OK. The VHDL <-> max2 utility generates the <design name>.vsm file for simulation with ViewSim in the sim subdirectory of the max2 directory.

5. If necessary, correct any errors in the VHDL Design File and recompile the project.

6. Simulate your project, as described in Performing a Timing Simulation with ViewSim Software.

| Go to Performing Timing Verification for EDIF Output Files (.edo) with MOTIVE & MOTIVE for Powerview Software or Performing Timing Verification of Verilog Output Files (.vo) with MOTIVE Software in these MAX+PLUS II ACCESSSM Key topics for related information.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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