## Using Cadence Synergy & MAX+PLUS II Software

The following topics describe how to use the Cadence Synergy software with MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Cadence Working Environment

- Software Requirements
- MAX+PLUS II/Cadence Interface File Organization
- Altera-Provided Logic & Symbol Libraries

### Design Entry

- #### Design Entry Flow

- #### Creating VHDL Projects

  - Creating VHDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
  - Entering Resource Assignments
    - Modifying the Assignment & Configuration File with the setacf Utility

- #### Creating Verilog HDL Projects

  - Creating Verilog HDL Designs for Use with MAX+PLUS II Software
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL
  - Entering Resource Assignments
    - Modifying the Assignment & Configuration File with the setacf Utility

### Synthesis & Optimization

- #### VHDL

  - Synthesizing & Optimizing VHDL Files with Synergy Software
  - Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility

- #### Verilog HDL

  - Synthesizing & Optimizing Verilog HDL Files with Synergy Software
  - Converting Verilog HDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt Utility

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Programming Altera Devices

| Go to the following topics , which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Cadence web site (http://www.cadence.com)

## Setting Up the MAX+PLUS II/Cadence Working Environment

To use MAX+PLUS® II software with Cadence software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Cadence interface is installed automatically when you install the MAX+PLUS II software on your computer. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Cadence Interface File Organization for information about the MAX+PLUS II/Cadence directories that are created during MAX+PLUS II installation.

| The information presented here assumes that you are using the C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Cadence interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Cadence software versions described in the MAX+PLUS II/Cadence Software Requirements.

2. Add the following environment variables to your .cshrc file:

   `setenv ALT_HOME /usr/maxplus2`

   `setenv CDS_INST_DIR` <Cadence system directory path>

3. Add the $ALT_HOME/cadence/bin and $CDS_INST_DIR/tools/bin directories to the `PATH` environment variable in your .cshrc file. Make sure these paths are placed before the Cadence hierarchy path.

4. Add /usr/dt/lib and /usr/ucb/lib to the `LD_LIBRARY_PATH` environment variable in your .cshrc file.

5. Create a new cds.lib file in your working directory or edit an existing one so that it includes all of the following lines that apply to the Cadence tools you have installed:

   `DEFINE alt_syn ${ALT_HOME}/simlib/concept/alt_syn`

   `DEFINE lpm_syn ${ALT_HOME}/simlib/concept/lpm_syn`

   `DEFINE alt_lpm ${ALT_HOME}/simlib/concept/alt_lpm`

   `DEFINE alt_mf ${ALT_HOME}/simlib/concept/alt_mf`

   `DEFINE alt_max2 ${ALT_HOME}/simlib/concept/alt_max2`

   `DEFINE alt_max2 ${ALT_HOME}/simlib/composer/alt_max2/alt_max2`

   `DEFINE alt_vtl $ALT_HOME/simlib/concept/alt_vtl/lib`

   `DEFINE altera $ALT_HOME/simlib/concept/alt_mf/lib`

   `SOFTINCLUDE $CDS_INST_DIR/tools/leapfrog/files/cds.lib`

   `DEFINE` <design name>`.`

6. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:

   `cp /usr/maxplus2/maxplus2.ini $HOME`

   `chmod u+w $HOME/maxplus2.ini`

   | The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as MAX+PLUS II symbol and logic function library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.

   Normally, you do not have to edit your local copy of maxplus2.ini because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

7. If you are using Concept on a Sun SPARCstation running SunOS, go to Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software to install the redifnet EDIF netlist reader utility.

8. If you are using Synergy software, edit the hdl.var file located in your working directory to include the following line:

   `DEFINE work` <design name>

9. Set up an appropriate directory structure for the tool(s) you are using. See the following topics for information:
   - Composer Project File Directory Structure
   - Concept & RapidSIM Local Work Area Directory Structure

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Cadence Software Requirements

The following table shows the software applications that are used to generate, process, synthesize, and verify a project with MAX+PLUS® II and Cadence software:

Cadence | Altera
--- | ---

version 97A: Concept Composer ValidCOMPILER concept2alt
vlog2alt
altout
VerilogLink
Synergy
HDL Direct (Concept 2.0 or later)
Non-Graphic Simulation Environment (SE)
RapidSIM, Verilog-XL, or Leapfrog
redifnet (SunOS only)

MAX+PLUS II
version 10.0

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Cadence software applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

## MAX+PLUS II/Cadence Interface File Organization

Table 1 shows the MAX+PLUS® II/Cadence interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation. For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

#### Table 1. MAX+PLUS II Directory Organization

Directory | Description
./lmf | Contains the Altera-provided Library Mapping File, cadence.lmf, that maps Cadence logic functions to equivalent MAX+PLUS II logic functions.
./examples/cadence | Contains the sample files for Cadence software discussed in these ACCESSSM Key Guidelines.
./cadence | Contains the AMPLE userware for the MAX+PLUS II/Cadence interface.
./simlib/concept/alt_max2 | Contains the MAX+PLUS II primitives, including `CARRY`, `CASCADE`, `EXP`, `GLOBAL`, `LCELL`, `SOFT`, `OPNDRN`, `DFFE` (D flipflop with Clock Enable), and `DFFE6K` (D flipflop with Clock Enable and both Clear and Preset for FLEX® 6000 devices only) for use with Concept software.
./simlib/composer/alt_max2 | Contains the MAX+PLUS II primitives, including `CARRY`, `CASCADE`, `EXP`, `GLOBAL`, `LCELL`, `SOFT`, `OPNDRN`, `DFFE` (D flipflop with Clock Enable), and `DFFE6K` (D flipflop with Clock Enable and both Clear and Preset for FLEX 6000 devices only) for use with Composer software.
./simlib/concept/alt_lpm | Contains the MAX+PLUS II megafunctions, including library of parameterized modules (LPM) functions, for use with Concept software.
./simlib/concept/max2sim | Contains the MAX+PLUS II/Concept simulation model library, max2_sim, for use with RapidSIM software.
./simlib/concept/alt_syn | Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Concept software, and the vlog2alt utility.
./simlib/composer/alt_syn | Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Composer software.
./simlib/concept/lpm_syn | Contains the Cadence LPM library, lpm_syn, for use with Synergy and Concept software.
./simlib/composer/lpm_syn | Contains the Cadence LPM library, lpm_syn, for use with Synergy and Composer software.
./simlib/concept/alt_mf | Contains the MAX+PLUS II VHDL logic function library. (`a_8count` is for the MAX® 7000 and MAX 9000 device families only.)
./simlib/concept/edifnet/templates | Contains template files for Concept directives, i.e., global.cmd, compiler.cmd, vloglink.cmd, verilog.cmd, and master.local.
./simlib/concept/alt_max2/verilogUdps | Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Concept software.
./simlib/composer/alt_max2/verilogUdps | Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Composer software.
./simlib/concept/alt_vtl ./simlib/composer/alt_vtl | Contains VITAL library source files for use with Concept or Composer software.
./simlib/composer/alt_max2/verilog | Contains simulation modules for all symbols in the alt_max2 Composer library.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index
- FLEX Devices
- MAX Devices
- Classic Device Family

## Altera-Provided Logic & Symbol Libraries

The MAX+PLUS® II/Cadence environment provides four logic and symbol libraries that are used for compiling, synthesizing, and simulating designs.

| You can create your own libraries of custom symbols and logic functions in Concept and Composer. You can use custom symbols to incorporate an EDIF Input File, Text Design File (TDF), or any other MAX+PLUS II-supported design file into a project. MAX+PLUS II uses the cadence.lmf Library Mapping File to map standard Concept or Composer symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you can create a custom LMF that maps your custom symbols to the equivalent MAX+PLUS II-supported design file. You must also specify the directory that contains the MAX+PLUS II-supported design file(s) as a user library with the MAX+PLUS II User Libraries command (Options menu). Go to "Library Mapping File" and "Cadence Library Mapping File (cadence.lmf)" in MAX+PLUS II Help for more information.

#### The alt_max2 Library

You can enter a Concept or Composer Design Architect schematic with primitives and macrofunctions from the Altera-provided symbol library alt_max2. The alt_max2 library includes 74-series macrofunctions and several MAX+PLUS II primitives with corresponding Verilog HDL simulation models for controlling design synthesis and fitting. It also includes four macrofunctions--`a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux`--that are optimized for different device families, and the `clklock` phase-locked loop megafunction, which is supported by some FLEX® 10K devices, with corresponding Verilog HDL and VHDL simulation models. See Table 1. Choose Old-Style Macrofunctions and/or Primitives from the MAX+PLUS II Help menu for more information on functions in the alt_max2 library.

#### The alt_lpm Library

The Altera-provided alt_lpm library, which is available for Concept and Verilog HDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. Other parameterized functions, including cycle-shared FIFO (`csfifo`) and cycle-shared dual-port RAM (`csdpram`) are also included. The LPM standard defines a set of parameterized modules (i.e., parameterized megafunctions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. The parameters you specify for each LPM function determine the simulation models that will be generated. After the design is completed, you can target the design to any device family. In designs created with Concept, the Altera alt_lpm library works only with HDL Direct and the hdlconfig utility. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions in the alt_lpm library.

#### The lpm_syn Library

The lpm_syn library contains the Altera-provided parameterized functions. The lpm_syn library is similar to the alt_lpm library, except that it contains VHDL and Verilog HDL logic functions for use with Synergy, Concept, and Composer software.

#### The alt_mf Library

Altera provides a VHDL logic function library, alt_mf, that currently includes four macrofunctions--`a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux`--for controlling design synthesis and fitting. These elements can be instantiated directly in your VHDL file. To designate that these logic functions should pass untouched through the EDIF netlist file to the MAX+PLUS II Compiler, you must select the Maintain attribute constraint for instances of these functions before running the Synergy software. These models allow you to perform functional VHDL simulation while maintaining an architecture-independent VHDL description.

Table 1 shows the MAX+PLUS II-specific logic functions.

Table 1. MAX+PLUS II-Specific Logic Functions
Macrofunctions Note (1) | Primitives
Name | Description | Name | Description | Name | Description
`8fadd` | 8-bit full adder | `LCELL` | Logic cell buffer | `EXP` | MAX® 5000, MAX 7000, and MAX 9000 Expander buffer
`8mcomp` | 8-bit magnitude comparator | `GLOBAL` | Global input buffer | `SOFT` | Soft buffer
`8count` Note (2) | 8-bit up/down counter | `CASCADE` | FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer | `OPNDRN` | Open-drain buffer
`81mux` | 8-to-1 multiplexer | `CARRY` | FLEX 6000, FLEX 8000, and FLEX 10K carry buffer | `DFFE DFFE6K` Note (3) | D-type flipflop with Clock Enable
`clklock` | Phase-locked loop

Notes:

1. Logic function names that begin with a number must be preceded by "`a_`" in VHDL designs. For example, `8fadd` must be specified as `a_8fadd`.

2. The `a_8count` logic function is for the MAX 7000 and MAX 9000 device families only.

3. For designs that are targeted to FLEX 6000 devices, you should use the `DFFE` primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the `DFFE6K` primitive.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

## Cadence Design Entry Flow

Figure 1 shows the design entry flow for the MAX+PLUS® II/Cadence interface.

#### Figure 1. MAX+PLUS II/Cadence Design Entry Flow

| Altera-provided items are shown in blue.

## Creating VHDL Designs for Use with MAX+PLUS II Software

You can create VHDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project. The MAX+PLUS II Text Editor offers the following advantages:

- VHDL templates are available with the VHDL Templates command (Templates menu). These templates are also available in the ASCII vhdl.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL design that can be synthesized and optimized with Synergy software, follow these steps:

1. You can instantiate the following MAX+PLUS II-provided logic functions in your VHDL design:

   - The alt_mf library contains the Altera® VHDL logic function library, which includes the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` macrofunctions. If you wish to instantiate alt_mf logic functions in your VHDL design, you must first compile this library, as described in Compiling the alt_mf Library.

   - The `clklock` megafunction, which enables the phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the `clklock` Megafunction in VHDL or Verilog HDL for information.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. If you wish to use Standard Delay Format (SDF) Output Files (.sdo) that contain timing information when performing post-compilation timing simulation with Leapfrog software, you must first compile the VITAL library source files, as described in Compiling the alt_vtl Library for for Use with Leapfrog Software.

3. (Optional) To enter resource assignments in your VHDL design, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.

4. After you have completed your VHDL design, synthesize and optimize it with Synergy software, as described in Synthesizing & Optimizing VHDL Files with Synergy Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files, the latter of which includes macrofunction instantiation.

- /usr/maxplus2/examples/cadence/example9/count4.vhd
- /usr/maxplus2/examples/cadence/example10/adder16.vhd

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating the clklock Megafunction in VHDL or Verilog HDL

MAX+PLUS® II interfaces to other EDA tools support the `clklock` phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility, which is available in the MAX+PLUS II system directory. Type `gencklk -h` at the DOS or UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).

The gencklk utility allows parameters for the `clklock` function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the `clklock` function name; therefore, the values do not need to be declared explicitly.

To instantiate the `clklock` megafunction in VHDL or Verilog HDL, go through the following steps:

1. Type the following command at the DOS or UNIX prompt to generate the `clklock_`x`_`y function, where x is the ClockBoost™ value and y is the input frequency in MHz:

   | Type `gencklk` <ClockBoost> <input frequency>`-vhdl` for VHDL designs.

   or:

   | Type `gencklk` <ClockBoost> <input frequency> `-verilog` for Verilog HDL designs.

   Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the `clklock` megafunction.

2. Create a design file that instantiates the `clklock``_`x`_`y.vhd or `clklock`_x_y.v file. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.

| In MAX+PLUS II version 8.3 and lower, running `genclklk` on a PC always creates files named as clklock.vhd, clklock.cmp, and clklock.v, regardless of the ClockBoost and input frequency values you specify.

Figures 1 and 2 show a `clklock` function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.

Figure 1. VHDL Design File with clklock Instantiation (count8.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY altera;
    USE altera.maxplus2.all;     --  Include Altera Component Declarations
    ENTITY count8 IS
       PORT (a    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             ldn  : IN STD_LOGIC;
             gn   : IN STD_LOGIC;
             dnup : IN STD_LOGIC;
             setn : IN STD_LOGIC;
             clrn : IN STD_LOGIC;
             clk  : IN STD_LOGIC;
             co   : OUT STD_LOGIC;
             q    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END count8;
    ARCHITECTURE structure OF count8 IS
       signal clk2x : STD_LOGIC;
    COMPONENT clklock_2_40
       PORT (
          INCLK : IN STD_LOGIC;
          OUTCLK : OUT STD_LOGIC
       );
    END COMPONENT;
    BEGIN
       u1: clklock_2_40
       PORT MAP (inclk=>clk, outclk=>clk2x);
       u2: a_8count
       PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
                 e=>a(4), f=>a(5), g=>a(6), h=>a(7),
                 clk=>clk2x,
                 ldn=>ldn,
                 gn=>gn,
                 dnup=>dnup,
                 setn=>setn,
                 clrn=>clrn,
                 qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
                 qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
                 cout=>co);
     END structure;

Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v)
    `timescale 1ns / 10ps
    module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q);
    output          co;
    output[7:0]     q;
    input[7:0]      a;
    input           ldn, gn,dnup, setn, clrn, clk;
    wire            clk2x;
    clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) );
    A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]),
                 .G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
                 .SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
                 .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
                 .QH(q[7]), .COUT(co) );
    endmodule

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

### Concept & Composer Schematics

In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility

Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments:

- /usr/maxplus2/examples/cadence/example6/fa2 (Concept)
- /usr/maxplus2/examples/cadence/example7/fa2 (Composer)

### VHDL & Verilog HDL Design Files

For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility.

| For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## Creating Verilog HDL Designs for Use with MAX+PLUS II Software

You can create Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for you project. The MAX+PLUS II Text Editor offers the following advantages:

- Verilog HDL templates are available with the Verilog Templates command (Templates menu). These templates are also available in the ASCII verilog.tmp file, which is located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your Verilog HDL design, you can use the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a Verilog HDL design that can be synthesized and optimized with Synergy software, go through the following steps:

1. You can instantiate the following MAX+PLUS II-provided logic functions in your Verilog HDL design:

   - The alt_max2 library, which contains the `a_8count`, `a_8mcomp`, `a_8fadd`, and `a_81mux` macrofunctions that are optimized for different Altera device families.

   - The `clklock` megafunction which enables phase-locked loop, or ClockLock™, circuitry available on selected Altera FLEX® 10K devices. Go to Instantiating the `clklock` Megafunction in VHDL or Verilog HDL for information.

   - The lpm_syn library, which contains the Cadence LPM megafunction library for use with Synergy Software and Concept or Composer software.

   - MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

2. You can enter resource assignments in your Verilog HDL design, as described in Entering Resource Assignments.

3. After you have completed your Verilog HDL design, synthesize and optimize it with Synergy software, as described in Synthesizing & Optimizing Verilog HDL Files with Synergy Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files, the latter of which includes LPM function instantiation.

- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating the clklock Megafunction in VHDL or Verilog HDL

MAX+PLUS® II interfaces to other EDA tools support the `clklock` phase-locked loop megafunction, which can be used with some FLEX® 10K devices, with the gencklk utility, which is available in the MAX+PLUS II system directory. Type `gencklk -h` at the DOS or UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).

The gencklk utility allows parameters for the `clklock` function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the `clklock` function name; therefore, the values do not need to be declared explicitly.

To instantiate the `clklock` megafunction in VHDL or Verilog HDL, go through the following steps:

1. Type the following command at the DOS or UNIX prompt to generate the `clklock_`x`_`y function, where x is the ClockBoost™ value and y is the input frequency in MHz:

   | Type `gencklk` <ClockBoost> <input frequency>`-vhdl` for VHDL designs.

   or:

   | Type `gencklk` <ClockBoost> <input frequency> `-verilog` for Verilog HDL designs.

   Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the `clklock` megafunction.

2. Create a design file that instantiates the `clklock``_`x`_`y.vhd or `clklock`_x_y.v file. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.

| In MAX+PLUS II version 8.3 and lower, running `genclklk` on a PC always creates files named as clklock.vhd, clklock.cmp, and clklock.v, regardless of the ClockBoost and input frequency values you specify.

Figures 1 and 2 show a `clklock` function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.

Figure 1. VHDL Design File with clklock Instantiation (count8.vhd)
    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY altera;
    USE altera.maxplus2.all;     --  Include Altera Component Declarations
    ENTITY count8 IS
       PORT (a    : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             ldn  : IN STD_LOGIC;
             gn   : IN STD_LOGIC;
             dnup : IN STD_LOGIC;
             setn : IN STD_LOGIC;
             clrn : IN STD_LOGIC;
             clk  : IN STD_LOGIC;
             co   : OUT STD_LOGIC;
             q    : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
    END count8;
    ARCHITECTURE structure OF count8 IS
       signal clk2x : STD_LOGIC;
    COMPONENT clklock_2_40
       PORT (
          INCLK : IN STD_LOGIC;
          OUTCLK : OUT STD_LOGIC
       );
    END COMPONENT;
    BEGIN
       u1: clklock_2_40
       PORT MAP (inclk=>clk, outclk=>clk2x);
       u2: a_8count
       PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
                 e=>a(4), f=>a(5), g=>a(6), h=>a(7),
                 clk=>clk2x,
                 ldn=>ldn,
                 gn=>gn,
                 dnup=>dnup,
                 setn=>setn,
                 clrn=>clrn,
                 qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
                 qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
                 cout=>co);
     END structure;

Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v)
    `timescale 1ns / 10ps
    module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q);
    output          co;
    output[7:0]     q;
    input[7:0]      a;
    input           ldn, gn,dnup, setn, clrn, clk;
    wire            clk2x;
    clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) );
    A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]),
                 .G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
                 .SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
                 .QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
                 .QH(q[7]), .COUT(co) );
    endmodule

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

### Concept & Composer Schematics

In both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility

Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments:

- /usr/maxplus2/examples/cadence/example6/fa2 (Concept)
- /usr/maxplus2/examples/cadence/example7/fa2 (Composer)

### VHDL & Verilog HDL Design Files

For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility.

| For information on entering assignments in the MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## Synthesizing & Optimizing VHDL Files with Synergy Software

You can use Cadence Synergy software to synthesize and optimize your VHDL files and convert them to EDIF input files that can be processed by the MAX+PLUS® II Compiler. The information presented here describes only how to use VHDL files that have been processed by Synergy software. For information on direct MAX+PLUS II support for VHDL Design Files, go to MAX+PLUS II VHDL Help.

To process a VHDL file with Synergy software for use with MAX+PLUS II software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Create a VHDL file <design name>.vhd using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software for more information on VHDL design entry.

3. Start Synergy by typing `synergy -lang vhdl` at a UNIX prompt from the working directory.

4. Analyze your source file <design name>.vhd:

   1. Choose Analyze Files (File menu) to open the Select Design dialog box.

   2. Click on the Analyze Files tab.

   3. Select the design name from the Files list.

   4. Choose Analyze to analyze the source file(s).

5. Choose the Select Design tab from the Select Design dialog box and specify the following options:

   1. Select the design architecture from the hierarchical list. The design architecture should appear in the Design box.

   2. Specify <design name>.run1 as the Run Directory.

   3. Type `alt_syn` as the Target Library name.

   4. (Optional) If you want to use the Synergy library of parameterized modules (LPM) synthesis capability, choose the Macro Libraries ellipse button and select lpm_syn in the Select From box.

6. (Optional) If you want to view a synthesized schematic in Concept or Composer, go through the following steps:

   1. Choose Schematic Generation (Utilities menu).

   2. Select either Concept or Composer in the Generate From box.

   3. Type `alt_max2` in the Symbol Libraries box.

   4. Choose Apply, then Close.

7. Choose the Select Design button from the Select Design window.

8. Indicate to the Synergy software that any `clklock` megafunction or any macrofunction instantiated in your VHDL design is a "black box" that must pass untouched through the EDIF netlist file:

   1. Choose Synthesis (Constraints menu), then choose Hierarchy Control.

   2. Select the module or instance name from the hierarchical View list for Module/Instance.

   3. Turn on Maintain Option in the Synthesis Constraints box.

   4. Select Module/Instance and Tree Below in the Apply To box.

   5. Choose Apply.

   6. Repeat steps a through e for each instance of the function.

9. Choose Synthesize (Synthesis menu) from the Synergy window and specify the following options:

   1. Click on the Synthesize tab.

   2. Turn on the Generate Schematic option.

   3. Select either Composer or Concept from the Type list box.

   4. Choose Synthesize to start synthesizing your design.

10. Generate an EDIF netlist file that can be compiled with MAX+PLUS II software, as described in Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility.

11. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files:

- /usr/maxplus2/examples/cadence/example9/count4.vhd
- /usr/maxplus2/examples/cadence/example10/adder16.vhd

## Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility

You can convert a VHDL design into an EDIF netlist file with the extension .edf. This file can then be imported into the MAX+PLUS® II software as an EDIF Input File (.edf).

To convert a VHDL design into an EDIF netlist file, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Synthesize and optimize your VHDL design with Synergy, as described in Synthesizing & Optimizing VHDL Files with Synergy Software.

3. Depending on whether or not you have installed the Concept alt_syn library, perform one of the following steps to create <design name>.edf in the working directory:

   | If you have installed the Concept alt_syn library, type the following command at the UNIX prompt from your working directory: `vlog2alt` <design name> `-rundir max2 -vfiles` <design name>`.run1/syn.v`

   or:

   | If you have not installed the Concept alt_syn library, follow these steps:

   1. Edit the cds.lib file, which is located in your working directory, to include the following line:

      `DEFINE Opt` <working directory>/<design name>`.run1/Opt`

   2. Type the following command at the UNIX prompt from the working directory:

      `altout -lib Opt -rundir max2` <design name>

4. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files:

- /usr/maxplus2/examples/cadence/example9/count4.vhd
- /usr/maxplus2/examples/cadence/example10/adder16.vhd

## Synthesizing & Optimizing Verilog HDL Files with Synergy Software

You can create and process Verilog HDL files and convert them into EDIF input files that can be processed by the MAX+PLUS® II Compiler. To process a Verilog HDL file with Synergy software for use with the MAX+PLUS II software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting up the MAX+PLUS II/Cadence Working Environment.

2. Create a Verilog HDL file <design name>.v using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating Verilog HDL Designs for Use with MAX+PLUS II Software for more information on Verilog HDL design entry.

3. Start Synergy by typing `synergy -lang verilog` at a UNIX prompt from your working directory.

4. Choose Select Design (File menu) from the Synergy window and specify the following options:

   1. Select <design name>.v from the Verilog Files list.

   2. Choose the Verilog Option tab from the Select Design dialog box.

   3. Specify <design name>.run1 as the Run Directory.

   4. Type `/usr/maxplus2/simlib/concept/alt_max2/`<design name>`/verilog_lib/verilog.v` <working directory>/ in the Library Files (-v) box.

   5. (Optional) If your design includes library of parameterized modules (LPM) functions, type `+define+SYNTH` in the Other Compilations box.

   6. Choose Select Design.

5. Choose the Design tab from the Select Design dialog box and set the target library:

   1. Type `alt_syn` as the Target Library name.

   2. (Optional) To use the Synergy LPM synthesis capability, type `lpm_syn` as the Library name in the Macro Cell Library box.

   3. Choose OK.

6. (Optional) To view the synthesized schematic in Concept or Composer, go through the following steps:

   1. Select Schematic Generation (Utilities menu).

   2. Select either Concept or Composer in the Generate From box.

   3. Type `alt_max2` in the Symbol Libraries box.

   4. Choose Apply, then Close.

7. Choose Select Design from the Select Design window.

8. Choose Synthesize (Synthesis menu) from the Synergy window and specify the following options:

   1. Click on the Synthesize tab.

   2. Turn on the Generate Schematic option.

   3. Select either Composer or Concept from the Type list box.

   4. Choose Synthesize to start synthesizing your design.

9. Generate an EDIF netlist file that can be compiled by the MAX+PLUS II Compiler, as described in Converting Verilog HDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files.

10. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files:

- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v

## Converting Verilog HDL Designs into MAX+PLUS II-
Compatible EDIF Netlist Files with the vlog2alt Utility

You can use the vlog2alt utility to convert your Verilog HDL design into an EDIF netlist file. This file can then be imported into the MAX+PLUS® II software as an EDIF Input File with the extension .edf.

To convert a Verilog HDL design into an EDIF netlist file, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Synthesize and optimize your Verilog HDL design with Synergy, as described in Synthesizing & Optimizing Verilog HDL Files with Synergy Software.

3. To convert your Verilog HDL design into an EDIF netlist file, type the following command at the UNIX prompt from your working directory:

   `vlog2alt <`design name>`-rundir max2 -vfiles` <design name>`.run1/syn.v`

4. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Verilog HDL files:

- /usr/maxplus2/examples/cadence/example11/count8.v
- /usr/maxplus2/examples/cadence/example13/rom_test.v

## Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

| Refer to the following sources for additional information:

- Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

- Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   | Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   | You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type `setacf -h` and `maxplus2 -h` for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      | If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than `VCC` or `GND` for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   - Exemplar Logic Galileo Extreme-Specific Compiler Settings
   - Synopsys DesignWare-Specific Compiler Settings
   - Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   - Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      | This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   | See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

- JEDEC Files (.jed)
- Programmer Object Files (.pof)
- SRAM Object Files (.sof)
- Hexadecimal (Intel-format) Files (.hex)
- Tabular Text Files (.ttf)

| Refer to the following sources for additional information:

- Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
- Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
- Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware

## Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS® II software, you can program an Altera® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

#### Figure 1. MAX+PLUS II Device Programming Flow

| Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

##### Table 1. Altera Programming Hardware

Programming Hardware Option | PCs | UNIX Work- stations | ACEX® 1K Devices | MAX® 3000A Devices | Classic® & MAX 5000 Devices | MAX 7000 & MAX 7000E Devices | MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000
&
MAX 9000A
Devices

FLEX® 6000,
FLEX 6000A,
FLEX 8000,
FLEX 10K,
FLEX 10KA,
FLEX 10KB,
&
FLEX 10KE Devices
In-System
Programming/
Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and
device-specific
adapters
BitBlaster™ Download Cable |  |  |  |  |  |  |  |  |
ByteBlasterMV™ Download Cable |  |  |  |  |  |  |  |  |
MasterBlaster™ Download Cable |  |  |  |  |  |  |  |  |

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

| Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
| Home | List by Vendor | List by Tool | List by Function | Cadence Topics | Synergy Topics | Documentation Conventions Copyright © 1995-2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.