## MAX 7000 & MAX 9000 Synthesis Example

The MAX® 7000 (including MAX 7000E, MAX 7000S, and MAX 7000A) and MAX 9000 device families have a sum-of-products architecture. To obtain optimum timing and area results, you can direct the Synopsys Design Compiler or FPGA Compiler software to synthesize your logic into a sum-of-products form. To assist the Synopsys compilers in meeting the timing and area constraints of your designs, the Altera® technology libraries provide models that approximate the timing of the MAX 7000 and MAX 9000 logic cells.

Figure 1 shows two timing models: the standard Altera MAX 7000 timing model and a Synopsys timing model that approximates the MAX 7000 model. The Synopsys model is built on the following three conditions and assumptions:

1. The combinatorial delay in logic cells has been equally divided between product terms and `OR` gates. Because the product-term delay equals the OR-gate delay, the Synopsys compilers treat them equally, producing a sum-of-products structure. On top of this structure, inverters are used where necessary.

2. A shared expander product term is always used to create combinatorial logic.

3. The Synopsys Design Compiler and FPGA Compiler software do not distinguish between array and global Clocks. Therefore, to estimate setup and hold timing most accurately, you must instantiate GLOBAL buffers to indicate a global clock in either your VHDL or Verilog HDL design.

Figure 1. Standard MAX 7000 Timing Model vs. Synopsys Approximation of Timing Model

If you wish to direct the Synopsys Design Compiler or FPGA Compiler software to produce sum-of-products logic that approximates the MAX 7000 or MAX 9000 timing model, you can type the following dc_shell prompt commands at the command line before compiling the design:

`set_structure false`

`set_flatten -effort low`

When `set_structure` is set to `false`, structuring is turned off, and the Synopsys Design Compiler and FPGA Compiler software cannot factor and share logic between functions. If you do not enter these commands, the Synopsys compilers may add logic, which can create additional area and timing delays.

Figure 2 shows a combinatorial design that is predictable when structuring is turned off, but is unpredictable when structuring is turned on.

Figure 2. Nonstructured vs. Structured Combinatorial Design

When you use `low` as the argument to the `set_flatten -effort` command, the Synopsys compilers use the shortest compilation time to create the sum-of-products implementation of your design. If you use the `medium` or `high` argument, the Synopsys compilers create optimally flattened designs, but usually require greater compilation time and offer little improvement in timing and area results.

You can type `report_timing` after compilation to view Synopsys-generated timing information.

If you wish to calculate the area of your design, you can obtain an approximate logic cell count in several ways. Altera recommends that you add the number of registers and combinatorial outputs in a design. Depending on your design, this number may be slightly lower than the final number reported by the MAX+PLUS II software.

To create a file detailing primitive usage in the design, type `report_reference>` <filename> after Synopsys compilation.

| To obtain accurate timing information about your design, you must use the MAX+PLUS II Timing Analyzer to analyze your design. For accurate area information, consult the Report File (.rpt) generated by the MAX+PLUS II software.

| Refer to the following sources for related information:

- Synopsys Design Compiler Reference Manual or Synopsys Command Reference Manual
- FPGA Compiler User Guide
- Synthesizing & Optimizing VHDL & Verilog HDL Pojects with Synopsys Software

  | Go to MAX Devices, which is available on the web, for additional information:

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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