## Synthesizing & Optimizing VHDL Files with Synergy Software

You can use Cadence Synergy software to synthesize and optimize your VHDL files and convert them to EDIF input files that can be processed by the MAX+PLUS® II Compiler. The information presented here describes only how to use VHDL files that have been processed by Synergy software. For information on direct MAX+PLUS II support for VHDL Design Files, go to MAX+PLUS II VHDL Help.

To process a VHDL file with Synergy software for use with MAX+PLUS II software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

2. Create a VHDL file <design name>.vhd using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software for more information on VHDL design entry.

3. Start Synergy by typing `synergy -lang vhdl` at a UNIX prompt from the working directory.

4. Analyze your source file <design name>.vhd:

   1. Choose Analyze Files (File menu) to open the Select Design dialog box.

   2. Click on the Analyze Files tab.

   3. Select the design name from the Files list.

   4. Choose Analyze to analyze the source file(s).

5. Choose the Select Design tab from the Select Design dialog box and specify the following options:

   1. Select the design architecture from the hierarchical list. The design architecture should appear in the Design box.

   2. Specify <design name>.run1 as the Run Directory.

   3. Type `alt_syn` as the Target Library name.

   4. (Optional) If you want to use the Synergy library of parameterized modules (LPM) synthesis capability, choose the Macro Libraries ellipse button and select lpm_syn in the Select From box.

6. (Optional) If you want to view a synthesized schematic in Concept or Composer, go through the following steps:

   1. Choose Schematic Generation (Utilities menu).

   2. Select either Concept or Composer in the Generate From box.

   3. Type `alt_max2` in the Symbol Libraries box.

   4. Choose Apply, then Close.

7. Choose the Select Design button from the Select Design window.

8. Indicate to the Synergy software that any `clklock` megafunction or any macrofunction instantiated in your VHDL design is a "black box" that must pass untouched through the EDIF netlist file:

   1. Choose Synthesis (Constraints menu), then choose Hierarchy Control.

   2. Select the module or instance name from the hierarchical View list for Module/Instance.

   3. Turn on Maintain Option in the Synthesis Constraints box.

   4. Select Module/Instance and Tree Below in the Apply To box.

   5. Choose Apply.

   6. Repeat steps a through e for each instance of the function.

9. Choose Synthesize (Synthesis menu) from the Synergy window and specify the following options:

   1. Click on the Synthesize tab.

   2. Turn on the Generate Schematic option.

   3. Select either Composer or Concept from the Type list box.

   4. Choose Synthesize to start synthesizing your design.

10. Generate an EDIF netlist file that can be compiled with MAX+PLUS II software, as described in Converting VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the vlog2alt or altout Utility.

11. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample VHDL files:

- /usr/maxplus2/examples/cadence/example9/count4.vhd
- /usr/maxplus2/examples/cadence/example10/adder16.vhd

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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