## Performing a Timing Simulation with ViewSim Software

After you have entered a design and compiled it with the MAX+PLUS® II Compiler, you can simulate a MAX+PLUS II-generated EDIF Output File (.edo) or VHDL Output File (.vho) with ViewSim software. ViewSim software can simulate both the functionality and the timing of your design. It also checks setup time, hold time, and Clock duty cycle timing requirements on registers.

To simulate a design with ViewSim software, follow these steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.

2. Compile the design with the MAX+PLUS II software and generate an EDIF Output File (.edo) or VHDL Output File (.vho), as described in Compiling Projects with MAX+PLUS II Software.

3. In the Viewlogic Cockpit window, choose Create (Project menu) to open the Create Project dialog box. Type the name of your working directory and choose OK. You must create this new directory to avoid overwriting your original files when you generate new files for simulation.

4. Choose SearchOrder (Project menu) and add the appropriate directories and aliases to your viewdraw.ini file if you have not already done so. Go to Viewlogic Powerview viewdraw.ini Configuration File for more information.

   | Refer to Viewlogic documentation for information on simulating projects that contain RAM functions. The procedure for reading an EDIF Output File and preparing it for simulation with ViewSim requires additional steps when the project contains RAM functions.

5. If you used the SCH <-> max2 or VHDL <-> max2 utility in the Max2 Express drawer to process your project, skip to step 8.

6. If you wish to simulate a VHDL Output File, follow the steps in Analyzing VHDL Files with the Vantage VHDL Analyzer then skip to step 7d.

7. If you are using the Altera® Toolbox Design Tools Drawer, follow these steps:

   1. To generate a Powerview wirelist from the EDIF Output File, double-click Button 1 on the max2_edifi icon in the Design Tools Drawer. The Netlist In dialog box is displayed.

   2. In the Netlist In dialog box, specify ../<design name> for the EDIF Netlist File option, then choose OK to process the EDIF netlist file.

   3. If your project is implemented in multiple devices, repeat steps a and b for each EDIF Output File generated by the MAX+PLUS II Compiler, and ensure that the Altera-provided alt_edif.cfg file is specified for the Attribute Swap Configuration File option. In a multi-device project, the MAX+PLUS II Compiler generates a separate file for each device, plus a top-level file that is identified by "_t" appended to the project name. You must also follow the steps in Using ViewDraw & ViewGen Software to Prepare for Multi-Device Board-Level Simulation with ViewSim Software.

   4. Start the vsm utility by double-clicking Button 1 on the max2_vsmnet icon in the Design Tools Drawer.

   5. Specify your design name for the Design Name option in the vsm dialog box and choose OK to generate the <design name>.vsm file.

8. Create a simulation command file (.cmd) for simulation with ViewSim software. Alternatively, you can enter commands at the prompt in the ViewSim window. Refer to your Viewlogic documentation for more information on creating ViewSim command files.

   | The Altera simulation model library, max2_sim, allows you to use the `alt_grst` signal to asynchronously clear all flipflops (`DFFE` primitives).

9. Start the ViewSim simulation tool by double-clicking Button 1 on the max2_VSim icon in the Design Tools Drawer or the Max2 Express Drawer.

10. Specify the following options in the ViewSim dialog box and choose OK to simulate the design:

    Option: | Setting:
    Design Name | <design name>
    Command File | <design name>.cmd
    VHDL Source Window | OFF
    VHDL Debugging | OFF

    ViewSim software simulates the design and starts the ViewTrace waveform editor to allow you to observe the simulation results.

| Refer to the following sources for related information:

- ViewSim documentation for complete details on simulating a project and using ViewTrace to observe waveform output results
- Using ViewDraw & ViewGen Software to Prepare for Multi-Device Board-Level Simulation with ViewSim Software

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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