## Setting Up Design Compiler & FPGA Compiler Configuration Files

The .synopsys_dc.setup configuration file allows you to set both Design Compiler and FPGA Compiler variables. The compilers read .synopsys_dc.setup files from three directories, in the following order:

1. The Synopsys root directory
2. Your home directory
3. The directory where you start the Design Compiler or FPGA Compiler software

The most recently read configuration file has highest priority. For example, a configuration file in the directory where you start the Design Compiler or FPGA Compiler software has priority over the other configuration files, and a configuration file in the home directory has priority over a configuration file in the root directory.

To set up your configuration files, follow these steps:

1. Add the lines shown in Figure 1 to your .synopsys_dc.setup configuration file. Altera provides a sample .synopsys_dc.setup file in the ./synopsys/config directory. Figure 1 shows an excerpt from that sample file.

   Figure 1. Excerpt from Sample .synopsys_dc.setup File
   `search_path = {./usr/maxplus2/synopsys/library/alt_syn/`<device family>`/lib};`
   `target_library = {`<technology library>`};`
   `symbol_library = {altera.sdb};`
   `link_library = {`<technology library>`};`
   `edifout_netlist_only = "true";`
   `edifout_power_and_ground_representation = "net";`
   `edifout_power_net_name = "VDD";`
   `edifout_ground_net_name = "GND";`
   `edifout_no_array = "false";`
   `edifin_power_net_name = "VDD";`
   `edifin_ground_net_name = "GND";`
   `compile_fix_multiple_port_nets = "true"`
   `bus_naming_style = "%s<%d>";`
   `bus_dimension_separator_style = "><";`
   `bus_inference_style = "%s<%d>";`

2. Specify one of the Design Compiler & FPGA Compiler Technology Libraries for the `target_library` and `link_library` parameters in the .synopsys_dc.setup file.

3. If you will instantiate architecture control logic functions from the alt_mf library, add the following line to your .synopsys_dc.setup file:

   `define_design_lib altera -path /usr/maxplus2/synopsys/library/alt_mf/lib`

   | If you wish to use the VHDL System Simulator (VSS) software to simulate a VHDL design containing alt_mf library functions, you must compile this library with the analyze_vss script. See Setting Up VSS Configuration Files for more information.

4. If you will use the DesignWare interface for FLEX® 6000, FLEX 8000, or FLEX 10K designs, enter additional lines in your .synopsys_dc.setup file, as described in Setting Up the DesignWare Interface.

5. Specify one of the following families for the <device family> variable in the `search_path` parameter: `max5000`, `max7000`, `max9000`, `flex6000`, `flex8000`, or `flex10k`.

6. If you wish to resynthesize a design for a different device family, modify the .synopsys_dc.setup file by following the steps described in Resynthesizing a Design Using the alt_vtl Library & a MAX+PLUS II SDF Output File.

| Go to MAX+PLUS® II/Synopsys Interface File Organization in these MAX+PLUS II ACCESSSM Key topics for related information.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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