## Using Mentor Graphics & Exemplar Logic Tools with MAX+PLUS II Software

The following topics describe how to use a variety of Mentor Graphics and Exemplar Logic tools as part of a complete design flow that includes the MAX+PLUS® II software. If you use only one Mentor Graphics or Exemplar Logic tool, click List by Tool and select the tool name to view the list of topics only for that tool. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

### Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

- Software Requirements
- Altera-Provided Logic & Symbol Libraries
- Local Work Area Directory Structure
- Mentor Graphics Project Directory Structure
- MAX+PLUS II Project Directory Structure
- MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

### Design Flow For All Mentor Graphics/Exemplar Logic Tools

### Design Entry

- #### Design Entry Flow

- #### Design Architect

- Creating Design Architect Schematics for Use with MAX+PLUS II Software

- Instantiating the clklock Megafunction in Design Architect Schematics
- Instantiating LPM Functions in Design Architect Schematics

- Entering Resource Assignments

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility
- BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols

- Creating Hierarchical Projects with Design Architect Software
- Performing a Functional Simulation with DVE & QuickSim II Software
- Performing a Functional Simulation with QuickHDL Pro Software
- Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility

- #### VHDL & Verilog HDL

- Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software

- Instantiating the clklock Megafunction in VHDL or Verilog HDL
- Instantiating LPM Functions in VHDL

- Entering Resource Assignments

- Modifying the Assignment & Configuration File with the setacf Utility

- Performing a Functional Simulation with QuickHDL Software
- Performing a Functional Simulation with QuickHDL Pro Software
- Creating Hierarchical Projects with Design Architect Software

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software
- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software

### Compilation

- Project Compilation Flow
- Compiling Projects with MAX+PLUS II Software

- Exemplar Logic Galileo ExtremeSpecific Compiler Settings

- Using the Altera Schematic Express (sch_exprss) Utility
- Using the Altera VHDL Express (vhd_exprss) Utility

### BackAnnotation

- BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols

### Simulation/Timing Analysis

- Project Simulation/Timing Analysis Flow
- Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation
- Performing a Timing Simulation with DVE & QuickSim II Software
- Performing a Timing Simulation with QuickHDL Software
- Performing a Timing Analysis with QuickPath Software

### Device Programming

- Programming Altera Devices

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Mentor Graphics web site (http://www.mentor.com)

## Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

To use the MAX+PLUS® II software with Mentor Graphics/Exemplar Logic software, you must install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Mentor Graphics/Exemplar Logic interface is installed automatically when you install the MAX+PLUS II software on your computer.

Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization for information about the MAX+PLUS II/Mentor Graphics directories that are created during MAX+PLUS II installation.

| The information presented here assumes that you are using a C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Mentor Graphics interface, follow these steps:

1. Ensure that you have correctly installed the MAX+PLUS II and Mentor Graphics software versions described in MAX+PLUS II/Mentor Graphics Software Requirements.

2. Add the following environment variables to your .cshrc file:

| `setenv ALT_HOME /usr/maxplus2`
| `setenv MGC_WD` <user-specified working directory>
| `setenv MGC_HOME` <Mentor Graphics system directory>
| `setenv MAX2_MENTOR /usr/maxplus2/mentor/max2`
| `setenv MGC_LOCATION_MAP` <user-specified location_map file>
| `setenv EXEMPLAR` <Galileo or Leonardo system directory>

| Installing the Altera®provided MAX+PLUS II/Mentor Graphics interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/.cshrc file.

3. Add the $MGC_HOME/bin, $MAX2_MENTOR/bin, $ALT_HOME/bin, $EXEMPLAR/bin/<os>, and $ALT_HOME/bin directories to the `PATH` environment variable in your .cshrc file, where <os> is the operating system, e.g., `SUN4` for SunOS; `SUN5` for Solaris.

4. If you plan to use the Altera Schematic Express (sch_exprss) utility or the Altera VHDL Express (vhd_exprss) utility, add the following environment variable to your .cshrc file:

| `setenv MAX2_QSIM /usr/maxplus2/simlib/mentor/max2sim`

5. Type `source ~/.cshrc` at a UNIX prompt to source the .cshrc file and validate the settings in steps 1 through 4.

6. Add the following lines to your MGC_location_map file:

| `$MAX2_MENTOR`
| `/usr/maxplus2/mentor/max2`
| `$MGC_GENLIB`
| `/`<user-specified Mentor Graphics GEN_LIB directory>
| `$MGC_LSLIB`
| `/`<user-specified Mentor Graphics LS_LIB directory>
| `$MAX2_EXAMPLES`
| `/`<user-specified example directory>
| `$MAX2_LMCLIB`
| `/`<user-specified Logic Modeling directory>
| `$MAX2_GENLIB`
| `/usr/maxplus2/simlib/mentor/alt_max2`
| `$MAX2_QSIM`
| `/usr/maxplus2/simlib/mentor/max2sim`
| `$MAX2_FONT`
| `/usr/maxplus2/mentor/max2/fonts`
| `$MGC_SYS1076_STD`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/ std`
| `$MGC_SYS1076_ARITHMETIC`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/arithmetic`
| `$MGC_SYS1076_PORTABLE`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/mgc_portable`
| `$MGC_SYS1076_IEEE`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/ieee`
| `$MGC_SYS1076_SRC`
| `/`<user-specified MGC_HOME directory>`/pkgs/sys_1076_std/` src
| `$MAX2_MFLIB`
| `/usr/maxplus2/simlib/mentor/alt_mf`

| Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/location_map/location_map file.

7. If you want to use QuickHDL software to simulate VHDL or Verilog HDL designs, add the following line in the `[library]` section of your quickhdl.ini file: `altera = $MAX2_MFLIB`.

8. If you plan to use QuickHDL software to simulate VITAL-compliant VHDL files, add the following lines to your MGC_location_map file:

| `$MAX2_VTLLIB`
| `/usr/maxplus2/simlib/mentor/alt_vtl`

9. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:

| `cp /usr/maxplus2/maxplus2.ini $HOME`
| `chmod u+w $HOME/maxplus2.ini`

| The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as Alteraprovided logic and symbol library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.
Normally, you do not have to edit your local copy of maxplus2.ini, because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Getting Started version 8.1 (5.4 MB)
- This manual is also available in 4 parts:
  - Preface & Section 1: MAX+PLUS II Installation
  - Section 2: MAX+PLUS II - A Perspective
  - Section 3: MAX+PLUS II Tutorial
  - Appendices, Glossary & Index

## MAX+PLUS II/Mentor Graphics Software Requirements

The following products are used to generate, process, synthesize, and verify a project with the MAX+PLUS® II software and Mentor Graphics software:

Mentor Graphics | Exemplar | Altera
--- | --- | ---

version C.2:
System_1076 Compiler QuickSim II Design Architect ENRead ENWrite
GEN_LIB library
QuickHDL
QuickHDL Pro
QuickPath
LS_LIB library (optional)
DVE

Leonardo Spectrum version 2000.1b
MAX+PLUS II
version 10.0

| The MAX+PLUS II read.me file provides up-to-date information on which versions of Mentor Graphics applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.

## Altera-Provided Logic & Symbol Libraries

The MAX+PLUS® II/Mentor Graphics environment provides libraries for compiling, synthesizing, and simulating designs.

| You can create your own libraries of custom functions for use in Design Architect schematics and VHDL and Verilog HDL design files. You can use custom functions to incorporate an EDIF Input File (.edf), Text Design File (.tdf), or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the Altera®provided mnt8_bas.lmf and exemplar.lmf Library Mapping Files to map standard Design Architect symbols and VHDL and Verilog HDL functions to equivalent MAX+PLUS II logic functions. To use custom functions, you can create a custom LMF that maps your custom functions to the equivalent EDIF input file, TDF, or other design file. Go to "Library Mapping File" in MAX+PLUS II Help for more information.

### Design Architect Libraries

You can enter a Design Architect schematic with logic functions from these Altera-provided symbol libraries: ALTERA LPMLIB, ALTERA GENLIB, LSTTL BY TYPE, and LSTTL ALL PARTS. You can access these libraries by choosing Altera Libraries (Libraries menu) in the Design Architect software. For information on using library of parameterized modules (LPM) functions, see ALTERA LPMLIB Library below.

### ALTERA GENLIB Library (Design Architect) & Altera (VHDL) Libraries

The ALTERA GENLIB symbol library (called the Altera library for VHDL) includes several MAX+PLUS II primitives for controlling design synthesis and fitting. It also includes four macrofunctions (`8count`, `8mcomp`, `8fadd`, and `81mux`) that are optimized for different Altera device families, and the `clklock` phase-locked loop megafunction, which is supported for some FLEX® 10K devices.

The following table shows the MAX+PLUS II-specific logic functions.

Table 1. MAX+PLUS II-Specific Logic Functions
Macrofunctions Note (1) | Primitives
Name | Description | Name | Description | Name | Description
`8fadd` | 8-bit full adder | `LCELL` | Logic cell buffer | `EXP` | MAX® 5000, MAX 7000, and MAX 9000 Expander buffer
`8mcomp` | 8-bit magnitude comparator | `GLOBAL` | Global input buffer | `SOFT` | Soft buffer
`8count` | 8-bit up/down counter | `CASCADE` | FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer | `OPNDRN` | Open-drain buffer
`81mux` | 8-to-1 multiplexer | `CARRY` | FLEX 6000, FLEX 8000, and FLEX 10K carry buffer | `DFFE DFFE6K` Note (2) | D-type flipflop with Clock Enable
`clklock` | Phase-locked loop

Notes:

1. Logic function names that begin with a number must be preceded by "`a_`" in VHDL designs. For example, `8fadd` must be specified as `a_8fadd` instead.
2. If you want to use QuickHDL software, make sure you have updated your quickhdl.ini file, as described in step 7 of Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
3. For designs that are targeted for FLEX 6000 devices, you should use the `DFFE` primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the `DFFE6K` primitive.

| Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions.

### ALTERA LPMLIB Library

The Alteraprovided ALTERA LPMLIB library, which is available for Design Architect schematics and VHDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. The LPM standard defines a set of parameterized modules (i.e., parameterized functions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. After the design is completed, you can target the design to any device family. The parameters you specify for each LPM function determine which simulation models are generated.

| Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX Devices
- Classic Device Family

## Local Work Area Directory Structure

Design Architect software automatically creates and maintains the project directory structure required for all stages of design entry. Galileo Extreme, Leonardo, and ENWrite software create a max2 subdirectory, if it does not already exist, under the project directory. These software applications also generate EDIF netlist files, and copy them from the <project name> directory to this max2 subdirectory. All MAX+PLUS® II Compiler output files are created in the max2 subdirectory.

Simulation files created with Mentor Graphics applications and Logic Modeling files are located in the board-level simulation subdirectory of the project directory. You can use these files during simulation with QuickSim II software.

The only directory you need to create is the local work directory, which should contain all project directories. Figure 1 shows the recommended file structure.

#### Figure 1. Recommended File Structure

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- MAX+PLUS II Project Directory Structure
- Mentor Graphics Project Directory Structure

## Mentor Graphics Project Directory Structure

Design Architect software generates the following files for each schematic:

- <drawing name>/mgc_component.attr
- <drawing name>/part.Eddm_part.attr
- <drawing name>/part.part_1
- <drawing name>/schematic.mgc_schematic.attr
- <drawing name>/schematic/schem_id
- <drawing name>/schematic/sheet1.mgc_sheet.attr
- <drawing name>/schematic/sheet1.sgfx_1
- <drawing name>/schematic/sheet1.ssht_1

The files generated for each schematic are stored in the schematic's <drawing name> directory and should not be edited. Mentor Graphics software automatically manages file storage and retrieval operations through this <drawing name> directory structure, which does not reflect hierarchical design relationships. Figure 1 shows a sample file structure with project1 as the UNIX project directory, and design1, subdesign1, and subdesign2 as the directories for the top-level design and subdesigns of the project.

Figure 1. Design Architect Project File Structure

When the ENWrite utility converts the schematic into an EDIF netlist file, it processes the design information and all related file subdirectories, then creates the EDIF netlist file in the directory defined by the user. The EDIF netlist file is named <project name>.edf, where <project name> is the name of the top-level design file. The <project name>.edf file is automatically moved to the max2 directory under the project directory.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Local Work Area Directory Structure
- MAX+PLUS II Project Directory Structure

## MAX+PLUS II Project Directory Structure

In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, VHDL, or Verilog HDL netlist file; an Altera Hardware Description Language (AHDL) Text Design File (TDF); or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by ENWrite, Galileo Extreme, or Leonardo software and imported into MAX+PLUS II as an EDIF Input File (.edf). Figure 1 shows an example of a MAX+PLUS II project directory.

Figure 1. Sample MAX+PLUS II Project Directory

The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Local Work Area Directory Structure
- Mentor Graphics Project Directory Structure

## MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

The following table shows the MAX+PLUS® II/Mentor Graphics interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation.

| For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

Table 1. MAX+PLUS II Directory Organization
Directory | Description
.lmf | Contains the Altera-provided Library Mapping Files, mnt8_bas.lmf and exemplar.lmf, that map Mentor Graphics and Exemplar Logic logic functions to equivalent MAX+PLUS II logic functions.
./mentor | Contains the AMPLE userware for the MAX+PLUS II/Mentor Graphics interface.
./simlib/mentor/alt_max2 | Contains MAX+PLUS II primitives such as `CARRY`, `CASCADE`, `EXP`, `GLOBAL`, `LCELL`, `SOFT`, `OPNDRN`, `DFFE`, and `DFFE6K` (D flipflop with Clock Enable) for use in Design Architect schematics.
./simlib/mentor/max2sim | Contains the MAX+PLUS II/Mentor Graphics simulation model library, max2sim, for use with QuickSim II and QuickPath software.
./simlib/mentor/synlib | Contains the MAX+PLUS II synthesis library for use with AutoLogic II software, which supports synthesis for users running Mentor Graphics version B1.
./simlib/mentor/alt_mf | Contains the MAX+PLUS II macrofunction and megafunction libraries.
./simlib/mentor/alt_vtl | Contains the MAX+PLUS II VITAL library.

## Altera/Mentor Graphics/Exemplar Logic Design Flow

The following figure shows the typical design flow for logic circuits created and processed with the MAX+PLUS® II and Mentor Graphics/Exemplar Logic software. Detailed diagrams for each stage of the design flow appear in Design Entry Flow, Project Compilation Flow, Project Simulation/Timing Analysis Flow, and Device Programming Flow.

## Mentor Graphics/Exemplar Logic Design Entry Flow

The following figure shows the design entry flow for the MAX+PLUS® II/Mentor Graphics/Exemplar Logic interface.

#### Figure 1. MAX+PLUS II/Mentor Graphics/Exemplar Logic Design Entry Flow

| Alteraprovided items are shown in blue.

## Creating Design Architect Schematics for Use with MAX+PLUS II Software

You can create Design Architect schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler.

To create a Design Architect schematic for use with MAX+PLUS II software, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Start the MAX+PLUS II/Mentor Graphics interface by typing `max2_dmgr` at a UNIX prompt.

3. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing `max2_da` at the UNIX prompt.

4. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to the following topics for more information:

- Local Work Area Directory Structure
- MAX+PLUS II Project Directory Structure
- Mentor Graphics Project Directory Structure

5. Choose the OPEN SHEET button in the Design Architect session_palette, then specify a name for your project in the Component Name box. Choose OK.

6. Enter logic functions from the following Altera®provided libraries:

- ALTERA LPMLIB includes library of parameterized modules (LPM) functions
- ALTERA GENLIB includes primitives and macrofunctions
- LSTTL includes 74-series macrofunctions

| You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPPSM). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

The following topics describe special steps needed to instantiate LPM and `clklock` functions:

- Instantiating LPM Functions in Design Architect Schematics
- Instantiating the clklock Megafunction in Design Architect Schematics

7. (Optional) To create a hierarchical design that contains symbols representing other design files, such as AHDL or VHDL design files, go to Creating Hierarchical Projects with Design Architect Software.

8. If you wish to make resource assignments in a Design Architect schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.

9. Choose Check Sheet for Altera (Check menu) to save and check your design. If your design contains LPM functions , the Design Architect software will ask whether you want to compile the LPM model. Choose YES if you want to compile the VHDL code for the LPM functions. The software will automatically select the corresponding compiler: System 1076 for B.(x) releases and QuickHDL compilers for releases C.1 and later.

10. (Optional) If your schematic design includes models for VHDL or Verilog HDL designs, perform a functional simulation with the QuickHDL Pro software, as described in Performing a Functional Simulation with QuickHDL Pro Software. If it does not, you can perform a functional simulation with the QuickSim software, as described in Performing a Functional Simulation with DVE & QuickSim II Software.

11. Once you have created a schematic, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:

- You can create an EDIF netlist file, as described in Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility.

- You can use the Altera Schematic Express utility, sch_exprss, to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and prepare the EDIF Output File for simulation with ENRead and Design Viewpoint Editor (DVE), as described in Using the Altera Schematic Express (sch_exprss) Utility.

Even if your design is a hierarchical design incorporating files created with multiple design entry methods, both the ENWrite and Altera Schematic Express utilities generate EDIF files for all files in the design.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample Design Architect schematic files:

- /usr/maxplus2/examples/mentor/example1/fulladd
- /usr/maxplus2/examples/mentor/example3/fulladd2
- /usr/maxplus2/examples/mentor/example7/fifo

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Instantiating the clklock Megafunction in Design Architect Schematics

You can instantiate the Altera®provided `clklock` phase-locked loop megafunction, which is supported for some FLEX® 10K devices, in a Design Architect schematic.

To instantiate the `clklock` megafunction in a Design Architect schematic, follow these steps:

1. Choose Altera Libraries (Library menu).

2. Choose ALTERA GENLIB (Altera Libraries menu).

3. Choose clklock (ALTERA GENLIB menu).

4. Specify appropriate values for the `CLOCKBOOST` and `INPUT_FREQUENCY` variables. Choose Megafunctions/LPM from the MAX+PLUS® II Help menu for detailed information on the `clklock` megafunction.

5. Choose OK.

6. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example7/fifo, which includes `clklock` megafunction instantiation.

| Go to FLEX 10K Device Family, which is available on the web, for additional information.

## Instantiating LPM Functions in Design Architect Schematics

Design Architect software allows you to instantiate functions included in the library of parameterized modules (LPM) from the ALTERA LPMLIB library.

Go through the following steps to instantiate LPM functions in a Design Architect schematic:

1. While you are entering your Design Architect schematic, choose Altera Libraries (Library menu).

2. Choose ALTERA LPMLIB (Altera Libraries menu).

3. Choose from the available LPM functions on the ALTERA GENLIB menu.

4. In the LPM_<function name> dialog box, specify appropriate values for the variables displayed for the LPM function you chose in step 3. Make sure that any hexadecimal (Intel-format) file that you use to specify the initial content of a memory function does not have the same name as the design file name. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on LPM functions.

5. Choose OK to generate a symbol for the LPM function you chose in step 3 and a corresponding VHDL simulation model.

6. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

7. When you save the schematic, the Design Architect software will ask whether you want to compile the LPM model. Choose YES if you want to compile the VHDL code for the LPM functions. The software will automatically select the corresponding compiler: System 1076 for B.(x) releases and QuickHDL compilers for releases C.1 and later.

Installing the Altera®provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example7/fifo, which includes LPM instantiation.

## Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

### Design Architect Schematics

In Design Architect schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility

| After you compile a project, you can back-annotate pin assignments, as described in BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example4/fa2, which includes resource assignments.

### VHDL & Verilog HDL Design Files

For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. Go to Modifying the Assignment & Configuration File with the setacf Utility for more information.

| Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Design Architect software. For information on entering assignments in MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).

## Assigning Pins, Logic Cells & Chips

You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device.

You can assign a signal to a particular pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. If you wish to set and maintain the performance of your project, assigning logic to a specific logic cell within a chip can minimize timing delays. In a project that is partitioned among multiple devices, you can assign logic functions that must be kept together in the same device to a chip. Chip assignments allow you to split a project so that only a minimum number of signals travel between devices, and to ensure that no unnecessary device-to-device delays exist on critical timing paths. You can assign a chip to a device in some EDA tools or in the MAX+PLUS® II software.

Use the following syntax for chip, pin, and logic cell assignments:

- To assign a logic function to a chip:

  `CHIP_PIN_LC=`<chip name>

  For example: `CHIP_PIN_LC=chip1`

- To assign a pin number within a chip:

  `CHIP_PIN_LC=`<chip name>`@`<pin number>

  For example: `CHIP_PIN_LC=chip1@K2`

- To assign a logic cell, I/O cell, or embedded cell number:

  `CHIP_PIN_LC=`<chip name>`@LC`<logic cell number>

  `CHIP_PIN_LC=`<chip name>`@IOC`<I/O cell number>

  `CHIP_PIN_LC=`<chip name>`@EC`<embedded cell number>

  For example: `CHIP_PIN_LC=chip1@LC44`

| Refer to the following sources for additional information:

- Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.

## Assigning Cliques

You can define a group of logic functions as a single, named unit, called a clique. The MAX+PLUS® II Compiler attempts to place all logic in the clique in the same logic array block (LAB) to ensure optimum speed. If the project does not use multi-LAB devices, or if it is not possible to fit all clique members into a single LAB, the clique assignment ensures that all members of a clique are placed in the same device. In FLEX® 6000, FLEX 8000, FLEX 10K, and MAX® 9000 devices the Compiler also attempts to place the logic in LABs in the same row. Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, and to ensure that no unnecessary LAB-to-LAB or device-to-device delays exist on critical timing paths.

| To assign a clique, use the following syntax: `CLIQUE=`<clique name> For example: `CLIQUE=fast1`

| Go to the following topics in MAX+PLUS II Help for related information:

- Assigning a Clique
- Guidelines for Achieving Maximum Speed Performance

## Assigning Logic Options

Logic option and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS® II Compiler also uses a device-family-specific default logic synthesis style for each project.

| Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments.

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols

The MAX+PLUS® II/Mentor Graphics software interface includes the annotate_pin utility. This utility allows you to back-annotate the pin assignments from the MAX+PLUS II-generated Fit File (.fit) back to the symbol for the design file. The annotate_pin utility has the following syntax:

`annotate_pin [-p` <property name>`]` <symbol name>`` <chip name>`` <Fit File name>

where <property name> is the default name for the pin assignment (default is `PIN_NO`), <symbol name> is the pathname of the directory that contains the symbol, <chip name> is the chip name specified in the Fit File, and <Fit File name> is the name of the Fit File that contains the pin assignment information for back-annotation. If the <property name> is not found at a pin number, that pin will not be back-annotated. If the <chip name> is not found in the Fit File, the annotate_pin utility stops the back-annotation process.

For example:

`annotate_pin -p PIN_NO /usr/examples/decode decode decode.fit`

| Type `annotate_pin -h` at the UNIX prompt to display information on how to use this utility.

## Creating Hierarchical Projects with Design Architect Software

If you wish to create a hierarchical schematic design that contains symbols representing other design files, such as AHDL Text Design Files (.tdf), VHDL Design Files (.vhd), or Verilog Design Files (.v), you can create a hollow-body symbol for the design file and then instantiate it in your top-level design file.

To create a hollow-body symbol for a lower-level design file, follow these steps:

1. (Optional) If you are creating a hollow-body symbol for a VHDL or Verilog HDL design file, you can first functionally simulate the VHDL or Verilog HDL file, as described in Performing a Functional Simulation with QuickHDL Software.

2. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing `max2_da` at the UNIX prompt.

3. Choose the OPEN SYMBOL button in the Design Architect session_palette to open the Symbol Editor. Type the lower-level design file name, including the directory path, in the Component Name box. Choose OK.

4. Create a symbol that represents the inputs and outputs of the lower-level file.

5. Assign `PINTYPE` properties of `IN` or `OUT` to the inputs and outputs of the symbol, and assign appropriate values to any other properties of the symbol so that it can be identified in the top-level schematic.

| If you are creating a hollow-body symbol for a VHDL design file, be sure to assign the value `qvpro` to the symbol's `model` property so that it can be identified as a VHDL component in the top-level schematic.

6. Check and save the symbol, then close the Symbol Editor.

7. To enter the symbol, choose the CHOOSE SYMBOL button from the Design Architect session_palette.

8. Select the symbol file from the Navigator menu and choose OK.

9. The MAX+PLUS® II software uses the Altera®provided mnt8_bas.lmf Library Mapping File to map Design Architect symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this LMF in the EDIF Netlist Reader Settings dialog box before compiling the design with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information.

10. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample hierarchical Design Architect schematic file /usr/maxplus2/examples/mentor/example3/fulladd2.

## Performing a Functional Simulation with DVE & QuickSim II Software

You can perform a functional simulation of a Design Architect schematic with the Mentor Graphics Design Viewpoint Editor (DVE) and QuickSim II software before compiling your project with the MAX+PLUS® II Compiler.

| If you wish to functionally simulate a hierarchical design that uses multiple design entry methods, you should use QuickHDL Pro rather than QuickSim. Refer to Performing a Functional Simulation with QuickHDL Pro Software for more information.

To functionally simulate a Design Architect schematic, go through the following steps:

1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a Design Architect schematic that follows the guidelines in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

3. In the Navigator window, select your project's folder, press Button 3, and choose Open max2_fve to start DVE. DVE checks the design and creates a viewpoint (called altera_fsim by default) for functional simulation with QuickSim II software.

4. Select the altera_fsim icon, press Button 3, and choose Open max2_qsim from the Navigator window to start the QuickSim II software. You can also start the QuickSim II software by typing `max2_qsim` at the UNIX prompt.

5. Set the appropriate options and simulate your design.

6. Use the ENWrite utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility.

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility

After you have created a Design Architect schematic or a hierarchical schematic design that uses multiple design entry methods, you can use the Mentor Graphics ENWrite utility to convert it into an EDIF netlist file that can be processed with the MAX+PLUS® II software.

To generate an EDIF netlist file for use with the MAX+PLUS II Compiler, go through the following steps:

1. Create a Design Architect Schematic that follows the guidelines described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

2. Select the folder for your project, press Button 3, and choose Open max2_enw from the Navigator window to open Design Viewpoint Editor (DVE), then ENWrite. You can also start the ENWrite utility by typing `max2_enw` at the UNIX prompt.

3. Choose OK in the $invoke_enw dialog box to accept the default names for the DVE viewpoint altera_edif, which is used internally by ENWrite, and the ENWrite hierarchical EDIF netlist file <design name>.edf. Specify OFF for the port array construct in the EDIF netlist file.

| The MAX+PLUS II software supports bus constructs in EDIF 2 0 0 and 3 0 0 netlist files, which allow you to retain any bus structures in your design. To preserve a bus in the EDIF netlist file, turn on the port array construct option in the $invoke_enw dialog box. However, if your design contains library of parameterized modules (LPM) functions, you should not use this feature because LPM 2.0.1 and 2.1.0 functions do not support EDIF bus constructs.

After DVE checks the Design Architect schematic, ENWrite generates <design name>.edf and automatically copies it to your project's directory.

4. Compile the resulting EDIF netlist file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

## Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software

You can create VHDL and Verilog HDL design files with the MAX+PLUS® II Text Editor or another standard text editor and save them in the appropriate directory for your project.

The MAX+PLUS II Text Editor offers the following advantages:

- Templates are available with the VHDL Templates and Verilog Templates commands (Template menu). These templates are also available in the ASCII vhdl.tmp and verilog.tmp files, respectively, which are located in the /usr/maxplus2 directory.

- If you use the MAX+PLUS II Text Editor to create your VHDL design, you can turn on the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.

To create a VHDL or Verilog HDL design file for use with the MAX+PLUS II software, go through the following steps:

1. Enter a VHDL or Verilog HDL design in the MAX+PLUS II Text Editor or another standard text editor and save it in your working directory.

2. Enter primitives, macrofunctions, and megafunctions in your VHDL or Verilog HDL design from the Altera library.

The following topics describe special steps needed to instantiate LPM and `clklock` functions:

- Instantiating LPM Functions in VHDL
- Instantiating the clklock Megafunction in VHDL or Verilog HDL

| You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP™). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software and Performing a Functional Simulation with QuickHDL Pro Software.

4. Once you have created a VHDL or Verilog HDL design, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:

- You can synthesize and optimize your design and create an EDIF netlist file, as described in Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software or Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software.

- You can use the Altera VHDL Express utility, vhd_exprss, to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and prepare the EDIF Output File for simulation with QuickHDL software, as described in Using the Altera Schematic Express (vhd_exprss) Utility.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL design files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Instantiating the clklock Megafunction in VHDL & Verilog HDL Designs

Altera provides the gencklk utility to allow you to instantiate `clklock` (phaselocked loop) functions in Mentor Graphics/Exemplar Logic software. The gencklk utility appends the parameter values to the `clklock` function name, so you don't need to declare attributes explicitly. The naming rule for the `clklock` function is `clklock_`<ClockBoost>`_`<inputfrequency>. The gencklk utility has the following syntax:

`gencklk` <ClockBoost>`` <inputfrequency>`[vhdl] [verilog]`

For the <ClockBoost> variable, you should specify a ClockBoost™ value of `1` or `2` (default value is `1`). For the <inputfrequency> variable, you should specify a decimal value in MHz (default value is `50`). To generate a VHDL file (which is the default if no option is present), specify `vhdl`; to generate a Verilog HDL file, specify `verilog`.

For example, to create the VHDL file clklock_2_50.vhd and the corresponding Component Declaration file clklock_2_50.cmp, type the following command at the UNIX prompt:

`gencklk 2 50 -vhdl`

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics interface on your computer automatically creates the sample VHDL design file /usr/maxplus2/examples/mentor/example6/count8.vhd, which includes `clklock` megafunction instantiation.

## Instantiating LPM Functions in VHDL

You can use Mentor Graphics Design Architect software to help you instantiate library of parameterized modules (LPM) functions in your VHDL design files.

To incorporate an LPM function into a VHDL design file, perform the following steps:

1. Be sure to set up the Design Architect working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Open a dummy schematic in the Design Architect software:

1. Start the Altera®/Mentor Graphics interface by typing `max2_dmgr` at a UNIX prompt.

2. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window.

3. Choose the OPEN_SHEET button in the Design Architect session_palette, then specify your project name in the Component Name box. Choose OK.

3. Instantiate the desired LPM function in the dummy schematic:

1. Choose Altera Libraries (Library menu).

2. Choose ALTERA LPMLIB (Altera Libraries menu).

3. Choose from the available LPM functions on the ALTERA LPMLIB menu.

4. In the LPM_<lpm function> dialog box, specify a name for the LPM function in the Cell Name box and appropriate values for the function's parameters. Make sure that any hexadecimal (Intel-format) file that you use to specify the initial content of a memory function does not have the same name as the design file name. Choose Megafunctions/LPM from the MAX+PLUS® II Help menu for detailed information about LPM functions.

5. Choose OK to generate the LPM function, the corresponding VHDL simulation model, and a VHDL Component Declaration/Attribute Declaration/Attribute Specification (.cmp) template.

4. Close the Design Architect software without saving the dummy schematic.

5. Instantiate the function created in step 2 in your design file. Use the template file to help prevent syntax and other errors.

6. Continue with the steps necessary to complete your design file, as described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS® II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample hierarchical VHDL design file /usr/maxplus2/examples/mentor/example8/adder16.vhd, which includes LPM function instantiation.

## Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

### Design Architect Schematics

In Design Architect schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

- Assigning Pins, Logic Cells & Chips
- Assigning Cliques
- Assigning Logic Options
- Modifying the Assignment & Configuration File with the setacf Utility

| After you compile a project, you can back-annotate pin assignments, as described in BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example4/fa2, which includes resource assignments.

### VHDL & Verilog HDL Design Files

For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. Go to Modifying the Assignment & Configuration File with the setacf Utility for more information.

| Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Design Architect software. For information on entering assignments in MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).

## Modifying the Assignment & Configuration File with the setacf Utility

Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type `setacf -h` at a UNIX or DOS prompt to get help on this utility.

## Performing a Functional Simulation with QuickHDL Software

You can use Mentor Graphics QuickHDL software to functionally simulate VHDL or Verilog HDL design files before compiling them with the MAX+PLUS® II Compiler.

| If you wish to functionally simulate a hierarchical design that uses multiple design entry methods, you should use QuickHDL Pro rather than QuickHDL. Refer to Performing a Functional Simulation with QuickHDL Pro Software for more information.

To functionally simulate a VHDL or Verilog HDL design, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design file that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Start Design Architect by double-clicking Button 1 on the max_da icon in the Design Manager tools window. You can also start Design Architect software by typing `max2_da` at the UNIX prompt.

4. Choose Lib (QuickHDL menu) and specify your work library name as the Work Library name. Choose OK.

5. Choose Map (QuickHDL menu) to map the instantiated function to the equivalent function in the Altera logic function library. Choose Set to specify altera as the Logical Name and $MAX2_MFLIB as the Physical Name. Choose OK.

6. Choose Compile (QuickHDL menu) and use the Navigator window to select the icon for your project. Specify your work library name as the Work Library name and select the Simulation setting in the Set VHDL Compilation Options or Set Verilog HDL Compilation Options window. Choose OK to compile.

7. Choose Simulate (QuickHDL menu) and specify your work library name as the Work Library name. Choose OK to start the QuickHDL Startup window.

8. Select the icon for your project in the Entity Configuration window and choose OK to simulate the design.

9. Synthesize and optimize the design, as described in Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software or Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software.

If your Verilog HDL design uses memory functions (RAM or ROM) that can be initialized with a hexadecimal file (Intel-format) initialization, you must convert these files into Verilog HDL format using the Programming Language Interface (PLI). To use the Altera-provided source code for PLI, perform the following steps:

1. Download the file http://www.edif.org/lpmweb/convert_hex2ver.c to your project directory.

2. Copy the following two files from the $MGC_HOME/shared/pkgs/quickhdl/include directory into the /usr/maxplus2 directory:

- $MGC_HOME/shared/pkgs/quickhdl/include/veriuser
- $MGC_HOME/shared/pkgs/quickhdl/include/acc_user

Refer to the Mentor Graphics QuickHDL User's Reference Manual, version 8.5-4.6i, for information on compiling the PLI application on different platforms and using the Verilog HDL PLI.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Performing a Timing Simulation with QuickHDL Software
- Performing a Functional Simulation with QuickHDL Pro Software

## Performing a Functional Simulation with QuickHDL Pro Software

You can use Mentor Graphics QuickHDL Pro software to functionally simulate mixed-level schematic and VHDL designs before compiling them with the MAX+PLUS® II Compiler.

Refer to Mentor Graphics Getting Started with QuickHDL Pro page 2-1 and 3-1 for compatible design configurations.

To functionally simulate a QuickHDL at Top Level design, follow the steps in Getting Started with QuickHDL Pro, Chapter 2.

To functionally simulate a QuickSim II at Top Level design, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
2. Create a schematic design using QuickHDL models. Refer to Creating Design Architect Schematics for Use with MAX+PLUS II Software.
3. Compile the QuickHDL model using the QuickHDL Compiler with the -qhpro_syminfo option. (This is done automatically for LPM functions if you choose to compile the LPM models when saving the schematic.)
4. Start Design Architect by double-clicking Button 1 on the max_da icon in the Design Manager tools window.
5. Choose Open from the File menu, then choose Sheet from the Open menu to open the top level schematic.
6. Select the symbol for the VHDL model and choose Begin Edit Symbol from the Edit menu.
7. Press Button 3 to display the the Design Architect pop-up menu. Choose Add Menu from the Other Menus menu, then choose Set VHDL Info. Choose Import from Entity to display the "Import Entity Info" dialog box.
8. Specify the following options in the "Import Entity Info" dialog box:

   1. QHDL InitFile: Specify your quickhdl.ini file.

   2. Library Logical Name: Click on Choose Library button and fill the "Choose VHDL Library" form with your work library.

   3. Entity Name: Click on Choose Entity button and select the name of your entity.

   4. Default Architecture: Click on Choose Arch button and select corresponding architecture for the entity.

   After filling in the above information, click on OK to close the form.

9. Check the symbol with defaults. If there are no errors, save the symbol with default registration by choosing Save Symbol from the File menu, then choose Default Registration.
10. Choose End Edit Symbol from the Edit menu to close the Symbol Editor session. In the schematic window, select the symbol you have just edited and choose Object from the Report menu, then choose All from the Selected menu. In the report transcript, make sure the MODEL property is set to qhpro to ensure that the model will work with QuickHDL Pro.
11. Select the folder for your project, press button 3, and choose Open max2_qvpro to start QuickHDL Pro. You can also start QuickHDL Pro by typing max2_qvpro at the UNIX prompt. In the QVHDL Pro System dialog box, make sure EDDM Design is selected for Invoke on and the correct path name is specified for the design. Choose OK to start the QuickHDL Pro. A QHPro (QuickSim II) window and a QHPro (QuickHDL) window appear on the screen.
12. Use the QuickSim II window to simulate the top level schematic and the QuickHDL window to simulate the VHDL portion of the design.

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Instantiating LPM Functions in Design Architect Schematics
- Performing a Functional Simulation with QuickHDL Software

## Creating Hierarchical Projects with Design Architect Software

If you wish to create a hierarchical schematic design that contains symbols representing other design files, such as AHDL Text Design Files (.tdf), VHDL Design Files (.vhd), or Verilog Design Files (.v), you can create a hollow-body symbol for the design file and then instantiate it in your top-level design file.

To create a hollow-body symbol for a lower-level design file, follow these steps:

1. (Optional) If you are creating a hollow-body symbol for a VHDL or Verilog HDL design file, you can first functionally simulate the VHDL or Verilog HDL file, as described in Performing a Functional Simulation with QuickHDL Software.

2. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing `max2_da` at the UNIX prompt.

3. Choose the OPEN SYMBOL button in the Design Architect session_palette to open the Symbol Editor. Type the lower-level design file name, including the directory path, in the Component Name box. Choose OK.

4. Create a symbol that represents the inputs and outputs of the lower-level file.

5. Assign `PINTYPE` properties of `IN` or `OUT` to the inputs and outputs of the symbol, and assign appropriate values to any other properties of the symbol so that it can be identified in the top-level schematic.

| If you are creating a hollow-body symbol for a VHDL design file, be sure to assign the value `qvpro` to the symbol's `model` property so that it can be identified as a VHDL component in the top-level schematic.

6. Check and save the symbol, then close the Symbol Editor.

7. To enter the symbol, choose the CHOOSE SYMBOL button from the Design Architect session_palette.

8. Select the symbol file from the Navigator menu and choose OK.

9. The MAX+PLUS® II software uses the Altera®provided mnt8_bas.lmf Library Mapping File to map Design Architect symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this LMF in the EDIF Netlist Reader Settings dialog box before compiling the design with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information.

10. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample hierarchical Design Architect schematic file /usr/maxplus2/examples/mentor/example3/fulladd2.

## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software

After you have created a VHDL or Verilog HDL design, you can use Exemplar Logic's Galileo Extreme software to synthesize and optimize your VHDL Design File (.vhd) or Verilog Design File (.v) and prepare it for compilation with the MAX+PLUS® II Compiler.

To synthesize and optimize your project and generate an EDIF netlist file with Galileo Extreme software, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software.

4. Select the icon for your design file in the appropriate directory, press Button 3, and choose max2_galileo in the Navigator window to start the Galileo Extreme software. You can also start Galileo Extreme software by typing `max2_galileo` at the UNIX prompt.

5. Specify settings for the Filename and Format options under INPUT DESIGN.

6. Specify settings for the Filename, Format, and Technology options under OUTPUT DESIGN. Verify that EDIF is specified in the Format box.

7. Choose the Altera Output Options button if you want to specify settings for various parameters, including Maximum Fanin for MAX devices and Part Number for FLEX devices. You can also turn on the Run MAX+PLUS II option for design compilation, which specifies that the MAX+PLUS II Compiler should start processing your design immediately after you run Galileo Extreme. Choose OK to save any setting changes.

8. Choose Start Run. The Galileo Extreme software generates <design name>.edf in the <project directory>/max2 subdirectory and then closes, returning you to the Navigator window.

9. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software. If you turned on the Run MAX+PLUS II option in step 7, the MAX+PLUS II Compiler automatically starts processing your design after you run Galileo Extreme.

Installing the Altera®provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL Design Files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software
- Performing a Timing Simulation with QuickHDL Software
- Performing a Timing Analysis with QuickPath Software

## Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software

After you have created a VHDL or Verilog HDL design, you can use Exemplar Logic's Leonardo software to synthesize and optimize your VHDL Design File (.vhd) or Verilog Design File (.v) and prepare it for compilation with the MAX+PLUS® II Compiler.

To synthesize and optimize your project and generate an EDIF netlist file with Leonardo software, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL or Verilog HDL design that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. (Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software.

4. Select the icon for your project's design file from the Navigator window, press Button 3, and choose max2_leonardo to start the Leonardo software and open the Exemplar Logic Leonardo window. You can also start Leonardo by typing `max2_leonardo` at the UNIX prompt.

5. Click Button 1 on the Flow Guide toolbar button to open the Customize Flow Guide dialog box.

6. Turn on the Altera EDIF Output File checkbox under Output Flow.

7. Choose Run Flow Guide to open the Flow Guide window and specify the appropriate options in the following modules to synthesize your project:

1. Choose Load Library to open the Load Library dialog box. If necessary, select FPGA Enhanced from the Tech Type drop-down list box. Select the target Altera® device family from the list of supported device families and choose Load to close the dialog box.

2. Choose Read to open the Read dialog box. Turn on VHDL or Verilog HDL under Format, ensure that the appropriate library name appears under Work Library, and type the name of your design file in the Filename box or select it from the Select a File dialog box. Choose Read to close the dialog box.

3. Choose Pre-Optimize to open the Pre-Optimize dialog box. Choose Pre-Optimize to accept the default pre-optimization settings and close the dialog box.

4. Choose Optimize to open the Optimize dialog box. Choose Optimize to accept the default optimization settings and close the dialog box.

5. Choose Write Altera to open the Convenience Procedures dialog box. Type `write_altera` in the Procedure box or select write_altera from the list box and choose Run to automatically generate <design name>.edf.

8. Choose Exit Flow Guide to return to the Leonardo window.

9. Process your design with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL Design Files:

- /usr/maxplus2/examples/mentor/example5/count4.vhd
- /usr/maxplus2/examples/mentor/example6/count8.vhd
- /usr/maxplus2/examples/mentor/example8/adder16.vhd

| Go to Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Project Compilation Flow

The following figure shows the MAX+PLUS® II/Mentor Graphics/Exemplar Logic project compilation flow.

#### Figure 1. MAX+PLUS II/Mentor Graphics/Exemplar Logic Project Compilation Flow

| Alteraprovided items are shown in blue.

## Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

| Refer to the following sources for additional information:

- Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

- Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

   | Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

   | You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type `setacf -h` and `maxplus2 -h` for descriptions of setacf and MAX+PLUS II command-line syntax.

4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

   1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

   2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      | If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

   3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

   4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than `VCC` or `GND` for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

   5. Choose OK.

6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:
   - Exemplar Logic Galileo Extreme-Specific Compiler Settings
   - Synopsys DesignWare-Specific Compiler Settings
   - Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
   - Synplicity Synplify-Specific Compiler Settings

8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

   1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      | This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

   2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

   3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

   4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

   | See step 3 for information on running MAX+PLUS II software from the command line.

10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

- JEDEC Files (.jed)
- Programmer Object Files (.pof)
- SRAM Object Files (.sof)
- Hexadecimal (Intel-format) Files (.hex)
- Tabular Text Files (.ttf)

| Refer to the following sources for additional information:

- Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
- Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
- Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
- Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware

## Exemplar Logic Galileo ExtremeSpecific Compiler Settings

If you are using MAX+PLUS® II software to compile a FLEX® design that was created with Galileo Extreme software, go through the following additional compilation steps:

1. Choose Global Project Logic Synthesis (Assign menu) to open the Global Project Logic Synthesis dialog box.

2. Select the appropriate logic synthesis style under Global Project Logic Synthesis Style:

| If you turned on the Lock Lcells option under SYNTHESIS SWITCHES in the Galileo Extreme Altera FLEX Output Options dialog box when synthesizing your design with Galileo Extreme software, select WYSIWIG in the Global Project Synthesis Style box.

or:

| If you did not turn on the Lock Lcells option, select FAST in the Global Project Synthesis Style box.

3. (Optional) Turning on one or more of the following options may help to improve area usage and timing delays:

- Automatic Fast I/O
- Automatic Register Packing
- (FLEX 10K devices only) Automatic Implement in EAB

4. Choose OK to close the Global Project Logic Synthesis dialog box.

5. Continue with the steps necessary to compile your project, as described in Compiling Projects with MAX+PLUS II Software.

| Go to the following topics, which are available on the web, for additional information:

- FLEX Devices
- MAX® Devices
- Classic Device Family

## Using the Altera Schematic Express (sch_exprss) Utility

Once you have created a Design Architect schematic, you can use the Altera Schematic Express utility (sch_exprss) to generate a Design Viewpoint Editor (DVE) viewpoint and an EDIF netlist file from the schematic; process the EDIF Input File (.edf) with the MAX+PLUS® II software to generate an EDIF Output File (.edo); process the EDIF Output File with ENRead and DVE software; and generate an altera_asim viewpoint for simulation. The sch_exprss utility creates all necessary subdirectories and copies all of the files to the correct locations.

To use the sch_exprss utility, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a Design Architect schematic that follows the guidelines described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

3. Select your project's folder, press Button 3, and choose Open sch_exprss from the Mentor Graphics Navigator window to start the Altera Schematic Express tool.

4. Specify settings for the Input Schematic, Altera Device Family, MAX+PLUS II Synthesis Style, Process Direction, and Verbose options in the sch_exprss dialog box and choose OK to generate the altera_asim file for simulation with QuickSim II software.

5. If necessary, correct any errors in the Design Architect schematic design file and recompile the project. The sch_exprss utility generates the altera_asim viewpoint in the appropriate directory.

6. Simulate your project, as described in Performing a Timing Simulation with DVE & QuickSim II Software.

| Go to Performing a Timing Analysis with QuickPath Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Using the Altera VHDL Express (vhd_exprss) Utility

Once you have created a VHDL Design File (.vhd) for your project, you can use the Altera® VHDL Express (vhd_exprss) utility to synthesize and optimize the design and generate an EDIF netlist file with Galileo Extreme software; process the EDIF netlist file with the MAX+PLUS II software to generate a VHDL Output File (.vho); and prepare the VHDL Output File for simulation with QuickHDL software. The vhd_exprss utility creates all necessary subdirectories and copies all files to the correct locations.

To use the vhd_exprss utility, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Create a VHDL Design File that follows the guidelines described in Creating VHDL & Verilog HDL Designs for Use with MAX+PLUS II Software.

3. Select the VHDL Design File for your project, press Button 3, and choose Open vhd_exprss from the Navigator window to start the Altera VHDL Express tool.

4. Specify settings for the Input HDL File, Altera Device Family, Max2 Synthesis Style, Process Direction, and Verbose options, and the Optimize and Effort runtime options, in the vhd_exprss dialog box, and choose OK.

5. If necessary, correct any errors in the VHDL Design File and recompile the project. The vhd_exprss utility generates a VHDL output file in the appropriate directory.

6. Simulate your project, as described in Performing a Timing Simulation with QuickHDL Software.

| Go to Performing a Timing Analysis with QuickPath Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## BackAnnotating MAX+PLUS II Pin Assignments to Design Architect Symbols

The MAX+PLUS® II/Mentor Graphics software interface includes the annotate_pin utility. This utility allows you to back-annotate the pin assignments from the MAX+PLUS II-generated Fit File (.fit) back to the symbol for the design file. The annotate_pin utility has the following syntax:

`annotate_pin [-p` <property name>`]` <symbol name>`` <chip name>`` <Fit File name>

where <property name> is the default name for the pin assignment (default is `PIN_NO`), <symbol name> is the pathname of the directory that contains the symbol, <chip name> is the chip name specified in the Fit File, and <Fit File name> is the name of the Fit File that contains the pin assignment information for back-annotation. If the <property name> is not found at a pin number, that pin will not be back-annotated. If the <chip name> is not found in the Fit File, the annotate_pin utility stops the back-annotation process.

For example:

`annotate_pin -p PIN_NO /usr/examples/decode decode decode.fit`

| Type `annotate_pin -h` at the UNIX prompt to display information on how to use this utility.

## Project Simulation/Timing Analysis Flow

The following figure shows the project simulation and timing analysis flow for the MAX+PLUS® II/Mentor Graphics interface.

Figure 1. MAX+PLUS II/Mentor Graphics Project Simulation/Timing Analysis Flow

| Alteraprovided items are shown in blue.

## Initializing Registers in VHDL & Verilog Output Files for Power-Up before Simulation

Altera provides the add_dc script, which is availiable in the MAX+PLUS II system directory, to allow you to process MAX+PLUS II-generated Verilog Output Files (.vo) and VHDL Output Files (.vho) to prepare these files for simulation with another EDA tool. The add_dc script runs the add_dclr utility, which inserts a `device_clear` signal that is used for power-up initialization of all registers or flipflops in the design.

The script adds in a top-level signal named `device_clear` and connects it to the `CLRN` pin in all flipflops that should initialize to 0, and to the `PRN` pin of all flipflops that should initialize to 1. If the `CLRN` or `PRN` pin of a flipflop is already being used (i.e., is already connected to a signal), the script modifies the Verilog Output File or VHDL Output File so that the `AND` of the original signal and the `device_clear` pin feed the `CLRN` or `PRN` pin.

To use the add_dc script to process Verilog Output Files and VHDL Output Files before simulation with another EDA tool, follow these steps:

1. Make sure that your design file is located in the current directory, or change to the directory in which the design file is located.

2. Type the following command at the command prompt:

   `\`<path name of add_dc.bat file>`\add_dc` <design name>`` <path name of add_dclr.exe file>

For example, if the both the add_dc.bat and the add_dclr.exe files are located in the d:\maxplus2\exew directory, and the d:\maxplus2\exew directory is specified in the search path, you can type the following command at a command prompt to add a `device_clear` signal to a design named `myfifo` in the file myfifo.vo:

`add_dc myfifo d:\maxplus2\exew`

1. The add_dc script gives a message if the directory contains both a VHDL Output File and a Verilog Output File with the same name (<design name>.vo and <design>.vho). You should delete or rename whichever of those files should not have the `device_clear` signal added. The add_dc script can modify only one design file at a time.

2. When the add_dc script processes the Verilog Output File or VHDL Output File, it creates a backup copy of the original file, with the extension .ori.

3. The add_dc script works only for Verilog Output Files and VHDL Output Files that are generated by MAX+PLUS II.

After you have used the add_dc script and are ready to simulate the resulting Verilog Output File or VHDL Output File with another EDA tool, you should assert the active low `device_clear` pin for a period of time that is long enough for the design to initialize. You can then de-assert the pin, and apply simulation vectors to the design.

## Performing a Timing Simulation with DVE & QuickSim II Software

After you have compiled a design with the MAX+PLUS® II Compiler, you can prepare the MAX+PLUS IIgenerated EDIF Output File (.edo) with Mentor Graphics Design Viewpoint Editor (DVE) and simulate it with the Mentor Graphics QuickSim II software.

To simulate an EDIF Output File with the QuickSim II software, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Generate an EDIF Output File for your project, as described in Compiling Projects with MAX+PLUS II Software or Using the Altera Schematic Express (sch_exprss) Utility.

3. If you used the Altera Schematic Express (sch_exprss) utility to process your design, skip to step 5. Otherwise, go to step 4.

4. In the Navigator window, select your project's icon, press Button 3, and choose Open max2_enr to read your project's EDIF Output File with the ENRead utility. You can also start ENRead software by typing `max2_enr` at the UNIX prompt.

5. Select your project's folder, press Button 3, and choose Open max2_ave to open DVE, which will prepare your project's simulation component for QuickSim II timing simulation. DVE automatically generates an appropriately named viewpoint for your project. You can also start DVE by typing `max2_ave` at the UNIX prompt.

6. Select your project's folder, press Button 3, and choose Open max2_qsim to simulate your project and its DVE viewpoint with QuickSim II software. You can also start QuickSim II by typing `max2_qsim` at the UNIX prompt.

7. In the Altera QuickSim dialog box, type the name of your project's viewpoint in the Viewpoint Name box. Select Timing as the Timing Mode. Select the Max timing option. Choose Scale Factor for Delay Scale, and be sure that `0.1` is specified for the Value. Choose OK.

| If the delay scale value is not set to 0.1 (i.e., divided by ten), the QuickSim II software will not reflect the correct timing simulation values.

| Go to Performing a Timing Analysis with QuickPath Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Preparing EDIF Output Files for Timing Simulation with Logic Modeling SmartModel Software

Once you have generated an EDIF Output File (.edo) for a design with the MAX+PLUS® II Compiler, you can use Logic Modeling SmartModel software to prepare it for simulation.

To use Logic Modeling SmartModel software, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Generate an EDIF Output File for your project, as described in Compiling Projects with MAX+PLUS II Software.

3. In the Navigator window, select your project's icon, press Button 3, and choose Open max2_lmi to start the Logic Modeling EDIF2SCF compiler and create a SmartModel Configuration Format File, as described in Creating a Logic Modeling SmartModel Configuration Format File.

4. Create a schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software, that contains an instance of a Logic Modeling SmartModel for the Altera® device specified in your project:

1. Start Design Architect by double-clicking on your project's icon in the Design Manager tools window.

2. Choose Altera Libraries (Libraries menu) and choose LOGIC MODELING (Altera Libraries menu). Select the appropriate device model for the Altera device specified in your project.

3. Change the `PLDFILE` property for the Altera device model to the full pathname of the SmartModel Configuration Format File generated in step 2.

4. Add pins to the device model.
5. Check and save the schematic in your project directory.

5. Select the icon for the folder representing the schematic generated in step 3, press Button 3, and choose Open max2_lve to open DVE and prepare your EDIF Output File for QuickSim II timing simulation. DVE generates a viewpoint named altera_lsim.

6. Select the icon for the folder representing the schematic generated in steps 2a through 2e, press Button 3, and perform a timing simulation on your project, as described in steps 5 and 6 of Performing a Timing Simulation with DVE & QuickSim II Software.

## Creating a Logic Modeling SmartModel Configuration Format File

The Logic Modeling SmartModel EDIF2SCF for Windows Compiler reads the <project name>.edo file generated by the MAX+PLUS® II Compiler and creates the <project name>.scf file. The EDIF2SCF compiler also extracts all state and internal net information for simulation of internal nodes (with the `x` and `w` options).

When the EDIF2SCF compiler opens, an Options prompt appears, providing options for the help_type, netlist_type, design_name, window_file, output_file, and interface_file. If some fields are not visible, press the TAB key to cycle through all six fields. The information you enter in these fields configures the EDIF2SCF compiler, and is equivalent to setting the various commandline options when compiling with EDIF2SCF.

Refer to the following table when setting options at the EDIF2SCF compiler's Options prompt. For information on these options, refer to EDIF2SCF Compiler in the Logic Modeling SmartModel Library Reference Manual.

Table 1. EDIF2SCF Options for Logic Modeling SmartModel
Setting(s) | Effect on EDIF2SCF
help_type option is turned on | Compiles with the `h` option
netlist_type option is set to extract | Compiles with the `x` option
netlist_type option is set to windows | Compiles with no options
netlist_type option is set to windows and the window_file option is set to the pathname of the windows definition file | Compiles with the `w` option
netlist_type option is set to windows and the output_file option is set to the pathname of a <filename>.scf file | Compiles with the `o` option
netlist_type option is set to windows and the interface_file option is set to the pathname of a custom <filename>.inf file | Compiles with the `i` option

## Performing a Timing Simulation with QuickHDL Software

After you have entered a VHDL or Verilog HDL design file and compiled it with the MAX+PLUS® II Compiler, you can use Mentor Graphics QuickHDL software to simulate the MAX+PLUS IIgenerated VHDL Output File (.vhd) or Verilog Output File (.vo) and the Standard Delay Format (SDF) Output File (.sdo).

To simulate your VHDL or Verilog HDL design, go through the following steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Generate a VHDL or Verilog HDL output file and an SDF output file for your project, as described in Compiling Projects with MAX+PLUS II Software.

3. Change to your project's directory.

4. Copy your quickhdl.ini file to the same directory as your VHDL or Verilog HDL file.

5. Type the following sets of commands at the UNIX prompt to create the work library and compile your project's VHDL or Verilog HDL output file:

VHDL: | Verilog HDL:
`setenv MGC_WD 'pwd'` `qhlib work` `qvhcom` <project name>`.vho` | `setenv MGC_WD 'pwd'` `qhlib work` `qvlcom` <project name>`.vo`

6. Type `qhsim -sdftyp` <project name>`.sdo` at the UNIX prompt to perform timing back-annotation and simulation and to display the QuickHDL simulation window.

If your Verilog HDL design uses memory functions (RAM or ROM) that can be initialized with a hexadecimal file (Intel-format) initialization, you must convert these files into Verilog HDL format using the Programming Language Interface (PLI). To use the Altera-provided source code for PLI, perform the following steps:

1. Download the file http://www.edif.org/lpmweb/convert_hex2ver.c to your project directory.

2. Copy the following two files from the $MGC_HOME/shared/pkgs/quickhdl/include directory into the /usr/maxplus2 directory:

   - $MGC_HOME/shared/pkgs/quickhdl/include/veriuser
   - $MGC_HOME/shared/pkgs/quickhdl/include/acc_user

Refer to the Mentor Graphics QuickHDL User's Reference Manual, version 8.5-4.6i, for information on compiling the PLI application on different platforms and using the Verilog HDL PLI.

| Go to Performing a Functional Simulation with QuickHDL Software in these MAX+PLUS II ACCESSSM Key topics for related information.

## Performing a Timing Analysis with QuickPath Software

After you have compiled your project with the MAX+PLUS® II Compiler and generated an EDIF Output File (.edo), you can use Mentor Graphics QuickPath software to perform a timing analysis of your project.

To perform a timing analysis with QuickPath software, follow these steps:

1. Be sure to set up the working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.

2. Generate an EDIF Output File for your project using one of the following methods:

- Compiling Projects with MAX+PLUS II Software
- Using the Altera Schematic Express (sch_exprss) Utility
- Using the Altera VHDL Express (vhd_exprss) Utility

3. Select your project's folder from the ALTERA directory, press Button 3, and choose Open max2_qpath to start the QuickPath software. You can also start the QuickPath software by typing `max2_qpath` at the UNIX prompt.

## Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS® II software, you can program an Altera® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

#### Figure 1. MAX+PLUS II Device Programming Flow

| Altera-provided items are shown in blue.

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

##### Table 1. Altera Programming Hardware

Programming Hardware Option | PCs | UNIX Work- stations | ACEX® 1K Devices | MAX® 3000A Devices | Classic® & MAX 5000 Devices | MAX 7000 & MAX 7000E Devices | MAX 7000A, MAX 7000AE, MAX 7000B, MAX 7000S MAX 9000
&
MAX 9000A
Devices

FLEX® 6000,
FLEX 6000A,
FLEX 8000,
FLEX 10K,
FLEX 10KA,
FLEX 10KB,
&
FLEX 10KE Devices
In-System
Programming/
Configuration
Logic Programmer card, PL-MPU Master Programming Unit, and
device-specific
adapters
BitBlaster™ Download Cable |  |  |  |  |  |  |  |  |
ByteBlasterMV™ Download Cable |  |  |  |  |  |  |  |  |
MasterBlaster™ Download Cable |  |  |  |  |  |  |  |  |

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

| Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- FLEX Devices
- MAX Devices
- Classic Device Family

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 |
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