## Using Synopsys Design Compiler or FPGA Compiler & MAX+PLUS II Software

The following topics describe how to use the Synopsys Design Compiler and FPGA Compiler software with the MAX+PLUS® II software. Click on one of the following topics for information:

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### Setting Up the MAX+PLUS II/Synopsys Working Environment

- Software Requirements
- Setting Up Design Compiler & FPGA Compiler Configuration Files
- Setting Up the DesignWare Interface
  - Updating DesignWare Libraries
- Libraries
  - Design Compiler & FPGA Compiler Technology Libraries
  - VHDL & Verilog HDL alt_mf Logic Function Library
  - DesignWare FLEX 6000, FLEX 8000 & FLEX 10K Synthetic Libraries
  - Post-Synthesis Libraries
- MAX+PLUS II/Synopsys Interface File Organization
- MAX+PLUS II Project File Structure

### Design Entry

- #### Design Entry Flow

- #### VHDL

  - Creating VHDL Designs for Use with MAX+PLUS II Software
    - Instantiating RAM & ROM Functions in VHDL (includes examples)
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL (includes examples)
  - Additional examples:
    - Primitive & Old-Style Macrofunction Instantiation Example for VHDL
    - Architecture Control Logic Function Instantiation Example for VHDL
    - DesignWare Up/Down Counter Function Instantiation Example for VHDL

- #### Verilog HDL

  - Creating Verilog HDL Designs for Use with MAX+PLUS II Software
    - Instantiating RAM or ROM Functions in Verilog HDL (includes examples)
    - Instantiating the clklock Megafunction in VHDL or Verilog HDL (includes examples)
  - Additional examples:
    - Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL
    - Architecture Control Logic Function Instantiation Example for Verilog HDL

### Synthesis & Optimization

- Synthesizing & Optimizing VHDL & Verilog HDL Projects with Synopsys Software
  - Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000, or FLEX 10K Devices
- Examples:
  - MAX 7000 & MAX 9000 Synthesis Example
  - DesignWare FLEX 8000 Synthesis Example
- Entering Resource Assignments
  - Assigning Pins, Logic Cells & Chips
  - Assigning Cliques
  - Assigning Logic Options
  - Modifying the Assignment & Configuration File with the setacf utility
  - Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
  - Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities
- Performing a Pre-Routing or Functional Simulation with VSS
- Resynthesizing a Design Using the alt.vtl Library & a MAX+PLUS II SDF Output File

| Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

- Compiling Projects with MAX+PLUS II Software
- Programming Altera Devices
- Using Synopsys FPGA Express & MAX+PLUS II Software
- Using Synopsys PrimeTime & MAX+PLUS II Software
- Using Synopsys VSS & MAX+PLUS II Software

| Go to the following topics, which are available on the web, for additional information:

- MAX+PLUS II Development Software
- Altera Programming Hardware
- Synopsys web site (http://www.synopsys.com)

Last Updated: JAugust 28, 2000 for MAX+PLUS II version 10.0 |
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