Solder Mask Optimization

Solder Mask Optimization is a read-write DFM action designed to increase yield by providing optimal clearances and optimal coverage wherever possible, and compromising only in dense places. It maintains clearances and coverage throughout the layer while keeping within the guidelines of the specified parameters.

The action enables modification of the solder mask layer to achieve manufacturing goals. ERF parameters and their definitions must be well understood in order to customize this action.

This action may be used on external signal layers and solder paste layers. Negative layers are inverted before processing. Drill layers passing through the signal layer and soldermask layers are referenced. Solder Mask Optimization has two operation modes:

*     Create Soldermask from scratch.    

*     Improve existing Soldermask.    

The following are the functions of the Solder Mask Optimization algorithm:

*    To provide optimal clearance for each pad.

*    For all over-exposed conductors (large soldermask opening), to increase coverage by shaving away a portion of the soldermask pad that is closest to the conductor, or by decreasing the size of soldermask clearance.

*     For adjacent pads from different nets, to provide a separating wall - a bridge (spacing between two SMD clearances) over a hole in the soldermask cover.

Terminology Bridge

A soldermask wall that separates two signal layer pads. Usually represented by a negative line placed over two adjacent pads.

Shave

A negative line placed over a pad to increase cover for a conductor.

Pad type

Can be a via, NPTH, SMD or fiducial feature, as derived from the feature's attribute, or the hole type drilled through the feature.

Positive Bridge

A positive line joining two soldermask clearances.

Violations

A violation is a relation between a signal layer feature and a soldermask feature that is not maintained according to design rules. For example, a clearance/space violation means that the space around the pad is less than that prescribed in the relevant parameter.

Clearance Classification
Small clearance - user-supplied clearance contained inside the signal layer pad.
Normal clearance - user-supplied clearance covering the signal layer pad but is covered by the optimal clearance.
Partial clearance - user- supplied clearance partially covering a pad.
Huge clearance - in at least one dimension the user-supplied clearance covers the pad with a margin of
v_max_oversized_clearance + pp_opt_clear or more.
Oversized clearance - in at least one dimension the user-supplied clearance covers the pad clearance with a margin of more than pp_opt_clear . (exceeds optimal clearance in some places).
Simple clearance - a single clearance for a single pad.
Single cover - it is possible to separate pads clearance from other clearances anyway. From all solder mask shapes touching the clearance a single one covers it completely. If it is not a Huge Clearance it is likely that it looks similar to the following:

We can process each clearance as a Simple Oversized clearance.

Multi feature clearance - a clearance which consists of more than one feature.
Usually it indicates drawn clearances and picture frames which cover several signal layer pads together.

 

Special Reports

Histograms for all categories are produced.

Result Attributes

The following attributes are produced once for each layer.

Attribute

Description

...Opt_Both

Violations (Optimal)

...Min_Both

Violations (Minimal)

...Bridges

Bridges (All)

...Opt_Cover

Opt.Cover Only

...Opt_Clear

Opt.Clear Only

...Too_Dense

Too dense

...Too_Tight

Problems

...Min_Bridge

Bridges (Violations)

...Large_Clears

Oversized Clearances

...Partials

Partial Clearances

...Small_Clears

Small Clearances

...Bridges_Pos

Bridges (Positive)

...Cannot_Bridge

Count all deleted Bridges

...Shaves

Count all Shaves

 

Cover to Clearance Compromise - Description

The essence of Solder Mask Optimization is the search for a best possible compromise between two opposing requirements:

1.      To provide sufficient clearance from soldermask for pads

2.      To provide sufficient soldermask coverage for conductors

In the best case, pads in external layers are far enough from conductors and from other nets. It is possible to specify wide clearances and still maintain a safe distance from the borders of the pads to neighboring conductors. But in more densely populated boards this is not the case: conductors are very close to pads and it is impossible to provide both the best possible coverage and the best possible clearance. Obviously, some kind of compromise between those two requirements must be reached.

Assume the following definitions:

opt_clear -  optimal clearance

min_clear - minimum acceptable clearance

opt_cover - optimal cover

min_cover - minimum acceptable cover.

Dist - distance between conductors that should stay covered and the shape which should be cleared.

All opt_clear,min_clear,opt_cover,min_cover are derived from corresponding parameters or from relevant range values.

Cover to Clearance compromise is solved differently for three cases, as follows:

1.       opt_clear + opt_cover <= dist

Both clearance and cover will be optimal.

2.      opt_clear + opt_cover > dist, but min_clear + min_cover < dist

Compromise may be reached without violating min_clear, min_cover .

If this value violates one of the minimums it is forced to the corresponding minimal value.

Example

 

3.      min_clear + min_cover > dist

The compromise will be reached according to the v_compromise variable in the following way:

SM Parameter Ranges

Starting from Software Version 2.0, the pad_to_drill_type dependency was limited to the following ERF variables:

*     v_enlarge_pth

*     v_enlarge_npth

*     v_enlarge_via

They define how much the corresponding clearance should be enlarged or reduced. If the resulting clearance radius is less than zero, no clearance will be produced.

We have added ranges of soldermask parameters according to pad type and drill type. Four different range types will be maintained:

*     SMD ranges

*     VIA ranges

*     PTH ranges

*     NPTH ranges.

A range definition includes its borders definition and a set of range parameters (values to control the Solder Mask Optimization process in this range).

The following restrictions will be applied to range definitions:

*     Maximum of 10 ranges can be defined for each type.

*     Range borders should not overlap.

*     Range parameter definition without corresponding range borders definition is invalid and ignored.

*     SMD ranges are classified according to the spacing between SMD pads of the same row (pitch - pad size) and VIA, PTH, NPTH ranges according to Annular Ring (distance to the closest signal layer feature).

For each range, the user may define how the range is partitioned between minimal clearance, optimal clearance, minimal coverage, and optimal coverage.

Also, a bridge value may be supplied for every range type. Ranges are numbered from 1 to 10 and three variables are defined for each range.

Range 1

For example, for range number 1 which covers SMD pads with pitches from 2 to 5 mils, the following ERF variables may be supplied:

-         # range number 1 covers pitches from 2 to 5 mils

-         SMD_1_BORDERS = 2:5

-         # min clearance is set to 20% of the spacing between SMD pads

-         # opt clearance is set to 60% of the spacing between SMD pads

-         # min coverage is set to 30% of the spacing between SMD pads

-         # opt coverage is set to 40% of the spacing between SMD pads

-         SMD_1_PARTITION = 0.2:0.6 0.3:0.4

-         # Bridge between SMD-features is 20% of the spacing between SMD pads

-         # in the row.

-         SMD_1_BRIDGE = 0.2

Range 2

For range 2, which covers SMD pads with pitches from 7 to 15 mils, the following ERF-variables may be supplied:

-         # range number 1 covers pitches from 2 to 5 mils

-         SMD_2_BORDERS = 7:15

-         # min clearance is set to 10% of the spacing between SMD pads

-         # opt clearance is set to 40% of the spacing between SMD pads

-         # min coverage is set to 30% of the spacing between SMD pads

-         # opt coverage is set to 10% of the spacing between SMD pads

-         SMD_2_PARTITION = 0.1:0.4 0.3:0.1

-         # Bridge between smd-features is 10% of the spacing between smd pads

-         # in the row.

-         SMD_2_BRIDGE = 0.1

Other Ranges

Ranges for other types are defined in the same way.

VIA_<x>_BORDERS = <from>:<to>

VIA_<x>_PARTITION = <min clearance>:<opt clearance> <min coverage>:<opt coverage>

VIA_<x>_BRIDGE = <bridge>

PTH_<x>_BORDERS = <from>:<to>

PTH_<x>_PARTITION = <min clearance>:<opt clearance> <min coverage>:<opt coverage>

PTH_<x>_BRIDGE = <bridge>

NPTH_<x>_BORDERS = <from>:<to>

NPTH_<x>_PARTITION = <min clearance>:<opt clearance> <min coverage>:<opt coverage>

NPTH_<x>_BRIDGE = <bridge>

Where <x> may be 1,2,.... 10 and stand for any range number.

Note: Any Annular ring value (or spacing value for SMDs) not covered by one of the ranges is treated according to the usual set of parameters:

pp_minimal_clearance

pp_optimal_clearance

pp_minimal_coverage

pp_optimal_coverage

pp_bridge.

If no ranges are defined, the Soldermask Mask Opt action functions exactly in the same manner as before.

For each clearance and pad type, default settings may be defined:

NPTH_BRIDGE = <bridge >

NPTH_PARTITION = <min clearance>:<opt clearance> <min coverage>:<opt coverage> will supply data in case only borders are defined for the range.

Additional details:

*     Delimiter may be any one of: , , ; :.

*     <min clearance> <= <opt clearance>

*     <min coverage> <= <opt coverage>

*     Only <min coverage> may be supplied in <XXXXX>_PARTITION statements.

*     <opt coverage> and <opt clearance> may be more than 1.

 

The following defaults are used:

*    If < opt clearance > is missing in the <XXXXX>_PARTITION statement, <opt clearance > is set to <min clearance>

*    If <min coverage> is missing in the <XXXXX>_PARTITION statement, <min coverage> is set to 1 - <opt clearance>

*    If <opt coverage> is missing in the <XXXXX>_PARTITION statement
<opt coverage > is set to <min clearance>