Panel Gold Plating Action

This chapter introduces the new Analysis action Panel Gold Plating . The action checks that all nets on a PCB that should be gold plated are shorted on the Panel step.

This action requires a new license option: pnlgpck .

Background

To ensure an efficient gold plating process, all nets which are to be gold plated must have a gold-tie connection which leads outside the profile of the PCB. When the PCB is panelized, all of these gold tie connections are then shorted together so they can be placed under current during the gold plating process. Since the connection (of gold ties) is done on the Panel level, there is no way to check the connections on the PCB level.

  
There are some NC processes (Drill or Rout) that are applied to the board only after the plating process. To ensure that the action does not interfere with these processes, the user can define which NC layers (drill or rout) should be ignored by the Panel Gold Plating process. Before the process starts, Panel Gold Plating will change temporarily the context of these "ignored" layers to "misc", then return them back to "board" context after the action finishes its run.

The analysis is run on the current step (Panel) and checks that all relevant nets of each PCB are connected on the current (Panel) step by touching copper on the Panel step.

Step-by-Step Process for Gold Plating Nets

The action checks for the layer nets that should be gold plated. This check is carried out on both sides of the board.

There are two ways to define a gold plated layer net:

By gold mask layer  -  a layer is used as a mask to mark the areas on the layer that should be plated by gold. Every layer net that is exposed by the mask layer is considered as a gold plated net.

Note: Clearance for soldermask is not considered in these calculations.

By attribute - user can specify which attribute is used to mark features that should be gold plated. If a layer net contains at least one feature assigned this attribute, it will be considered as a gold plated net.

  1. The action checks, for each PCB instance, that all gold plated nets touch copper on the current step. Any gold plated net that does not touch copper will be reported.
  2. The action checks for spacing violations between the drill holes of the current step and the gold plated nets. This process is repeated for nested steps - up to the PCB level.